Static Timing Analysis Design Engineer

European Tech Recruit; Cork; Sur place; EUR 85 000 - 120 000; Plein temps

Résumé du poste

European Tech Recruit are working closely with a multinational semiconductor technology company, based in Cork, who are looking for an experienced Static Timing Analysis Design Engineer to join their team.

As an STA Engineer, you will perform static timing analysis, develop timing constraints, and optimize timing performance for high-performance, low-power products. Collaboration across cross-functional teams will ensure timing closure and model validation.

Qualifications

• Experience in static timing analysis and timing closure for large SoCs or complex cores.
• Hands-on with STA tools for hierarchical analysis in large ASICs.
• Automation experience using Python, TCL or Perl.
• Solid knowledge of ASIC design flows (RTL-to-GDS).
• Interest in Design for Parametric Yield is a plus.

Responsabilités

• Perform STA and timing closure for complex cores and full-chip SOCs.
• Enhance techniques and methodologies for STA and timing closure.
• Drive accuracy of timing closure and timing flows to reduce turnaround time.
• Ensure compliance with timing signoff criteria.
• Automate timing and power data mining and processing.
• Participate in project proposal development with milestones and deliverables.
• Deliver project goals with production support and timely execution.
• Resolve issues across development phases to ensure smooth execution.

Connaissances

Strong communication

Outils

PrimeTime

PrimeShield

Tempus

Tweaker

PrimeClosure

PTECO

Tempus ECO

Python

TCL

Perl

Description du poste

European Tech Recruit are working closely with a multinational semiconductor technology company, based in Cork, who are looking for an experienced Static Timing Analysis Design Engineer to join their team.

As an STA Engineer, you will perform static timing analysis, develop timing constraints, and optimize timing performance for a variety of high-performance, high-quality, low-power world-class products. You will collaborate with cross-functional teams to ensure timing closure and validate timing models, contributing to the successful execution of product development.

Responsibilities as Static Timing Analysis Design Engineer:

• Performing STA and timing closure for complex cores and full-chip SOCs.
• Enhancing techniques and methodologies for STA and timing closure.
• Driving accuracy of timing closure and static/dynamic flows to reduce turnaround time.
• Ensuring compliance with timing signoff checklists and criteria.
• Automation for timing and power data mining and processing.
• Participating in project proposal development including key milestones and deliverables.
• Executing and delivering project goals in a timely manner with production support.
• Resolving issues in all phases of development to ensure smooth project execution.

Requirements:

• Expertise in STA tools (PrimeTime, PrimeShield or Tempus) used for hierarchical analysis in large SoCs.
• Hands-on experience with Tweaker, PrimeClosure, PTECO, or Tempus ECO for timing closure.
• Highly proficient in automation: Python, TCL or Perl.
• Strong knowledge of ASIC design flows (RTL-to-GDS).
• Interest in Design for Parametric Yield is an added advantage.
• Comfortable with extraction, circuit simulation tools and environments is a plus.
• Excellent problem-solving skills and result-driven approach, able to work and drive practical solutions under research environment.
• Good communication and personal skills in a multi-disciplinary, fast-paced engineering environment.

By applying to this role you understand that we may collect your personal data and store and process it on our systems. For more information please see our Privacy Notice (https://eu-recruit.com/about-us/privacy-notice/).