Senior Verification Engineer - Multimedia IP & SoCs

Qualcomm; Cork; On-site; EUR 65,000 - 90,000; Full time

Benefits offered by this job

Salary, stock and performance related

Maternity/Paternity Leave

Employee stock purchase scheme

Matching pension scheme

Education Assistance

Relocation and immigration support

Life, Medical, Income and Travel Insur

Subsidised memberships for physical/​m

Bicycle purchase scheme

Employee run clubs

Job summary

QT Technologies Ireland Limited is seeking a Verification Engineer to understand and verify multimedia designs, focusing on Computer Vision hardware IP and subsystems for SoCs in mobile applications.

You will work with architects, ASIC designers and SW engineers to plan verification strategies, develop testbenches in SystemVerilog/UVM, and contribute to test automation and documentation under supervision.

Qualifications

• Master’s degree or above with 2+ years in ASIC design and verification.
• Experience with test planning, debugging, and multimedia hardware verification.
• Hands-on with SystemVerilog/UVM and coverage-driven verification.

Responsibilities

• Architect and implement testbenches to verify multimedia IP.
• Create and maintain SystemVerilog/UVM test environments.
• Collaborate with Architecture, Software, Firmware, and Design teams to define test methodology and content.
• Participate in micro-architecture reviews.
• Develop automated CI/test content and support integration with IPs.
• Write technical docs and feature descriptions for straightforward projects.

Skills

SystemVerilog

UVM

Verilog

C/C++

Python scripting

Tcl/Perl scripting

Education

Bachelor's degree in Science/Engineering

Master's degree in Science/Engineering

PhD in Science/Engineering

Tools

AMBA AXI/ABP/AXI

SystemVerilog testbench automation

Job description

QT Technologies Ireland Limited is seeking a Verification Engineer to understand and verify multimedia designs, focusing on Computer Vision hardware IP and subsystems for SoCs in mobile applications.

You will work with architects, ASIC designers and SW engineers to plan verification strategies, develop testbenches in SystemVerilog/UVM, and contribute to test automation and documentation under supervision.