EVA Design Verification Engineer, Senior - Cork, Ireland

QUALCOMM, Inc.; Cork; Sur place; EUR 60 000 - 90 000; Plein temps

Avantages offerts par ce poste

Salary and performance-related bonus

Maternity/Paternity Leave

Employee stock purchase scheme

Matching pension scheme

Education Assistance

Relocation and immigration support

Life, Medical, Income and Travel Ins.

Subsidised memberships for well-being

Bicycle purchase scheme

Employee clubs

Résumé du poste

QT Technologies Ireland Limited in Cork invites a Verification Engineer to verify multimedia computer vision IP for SoCs. You will develop and maintain SystemVerilog/UVM testbenches, collaborate with architecture, software, firmware and design teams, and contribute to system-level test content and CI automation.

The role emphasises micro-architecture reviews, test methodology, and documentation of features under supervision.

Qualifications

• 2+ years of ASIC design and verification tools, techniques, and methodology.
• Test planning, problem solving, debugging, and verification of multimedia hardware.
• Strong knowledge of HVLs and OO programming (SystemVerilog, Verilog, C/C++, Tcl/Perl/Python).
• 2+ years building block-level testbench environments using SystemVerilog (coverage-driven).
• Experience with UVM/OVM and exposure to assertion-based formal verification.
• 2+ years scripting/automation using Perl or Python.

Responsabilités

• Architect and design testbenches to verify multimedia computer vision IP.
• Create and maintain verification environments in SystemVerilog/UVM.
• Collaborate with Architecture, Software/Firmware, Design and Validation teams to define test content.
• Participate in micro-architecture reviews.
• Collect and execute system-level tests including directed tests and compliance suites.
• Build CI/test automation for IP verification workflows.
• Document features and test plans under supervision.

Connaissances

SystemVerilog

UVM

C/C++

Verilog

Python

OO programming

Formation

Master’s degree in Computer Science/Engineering

Bachelor’s degree in Science/Engineering

PhD in Science/Engineering

Outils

AMBA AXI/AHB/APB

SystemVerilog testbenches

Description du poste

Company:

QT Technologies Ireland Limited

Job Area:

Engineering Group, Engineering Group > ASICS Engineering

General Summary:

As a Verification Engineer, you will be responsible for understanding the expected functionality of multimedia designs, specifically Computer Vision hardware IP and subsystem. You will work with the architects of these multimedia systems, as well as multimedia ASIC designers and SW engineers to plan and execute verification and validation of multimedia subsystems for integration into SoCs for mobile applications.

Responsibilities:

• Applies knowledge and experience to architect, design, implement, the testbench to verify the structure and performance computer vision IPs
• Creates and maintains verification test benches and environments in System Verilog/UVM
• Collaborates with Architecture, Software, Firmware, Design, Modeling, Emulation and Post-silicon validation teams to define and develop test methodology and content
• Participate in micro-architecture reviews
• Collect, organize and execute various forms of system level test content including directed testcases, standards compliance test suites, and system level scenarios
• Build automation for continue integration and testing based on latest IP
• Works with team members to understand and align on narrow scope of feature development and meet targets.
• Write technical documentation and feature descriptions for straightforward projects under the direction of a supervisor.

Qualifications:

• Master’s degree in Computer Science, Electrical Engineering, Computer Engineering, or a closely related field
• 2+ years of experience with ASIC design and verification tools, techniques, and methodology
• Test planning, problem solving, debug, Verification of Multi-media hardware
• Strong working knowledge of HVLs: System Verilog, OO programming. Verilog , C/C++, Tcl/Perl/python/shell-scripting
• 2+ years of experience with developing block-level testbench environment using SystemVerilog. Strong experiences in coverage-driven constrained random verification is preferred.
• 2+ years of experience with verification methodologies through coursework or past experiences such as UVM or OVM and exposure to Assertion based Formal Verification
• 2+ years of experience with scripting/automation skills using either Perl or python
• Experience with AMBA Bus protocol (AXI/AHB/APB etc) is desirable (not mandatory)
• Knowledge or experience with Assertion Based Formal Verification is desirable (not mandatory)
• Experience in formal verification is plus

Where you will be working

Cork has a proud reputation as Ireland's second largest economic engine and is now one of the Top 20 location choices in Europe with 39,000 people being employed by over 170 overseas companies.

There's a growing diversity in the region with people from many nationalities relocating to Cork, relishing the opportunity to work and live in a location that offers an excellent quality of life.

A gateway to Europe, Cork airport provides access to almost 50 international destinations including transatlantic air routes.

Equal Opportunities

We are an Equal Opportunity employer; all qualified applicants will receive consideration for employment without regard to race, colour, religion, sexual orientation, gender identity, national origin, disability, veteran status, or any protected classification.

What's on Offer

• Salary, stock and performance related bonus
• Maternity/Paternity Leave
• Employee stock purchase scheme
• Matching pension scheme
• Education Assistance
• Relocation and immigration support (if needed)
• Life, Medical, Income and Travel Insurance
• Subsidised memberships for physical and mental well-being
• Bicycle purchase scheme
• Employee run clubs, including, running, football, chess, badminton + many more

Minimum Qualifications

• Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
• Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
• PhD in Science, Engineering, or related field.

*References to a particular number of years experience are for indicative purposes only. Applications from candidates with equivalent experience will be considered, provided that the candidate can demonstrate an ability to fulfill the principal duties of the role and possesses the required competencies.