Senior Timing Engineer: ASIC Timing & P&R Specialist

Qualcomm; Ireland; On-site; EUR 70,000 - 110,000; Full time

Benefits offered by this job

Salary & stock bonus

Maternity/Paternity Leave

Employee stock purchase scheme

Pension matching

Education assistance

Relocation support

Job summary

QT Technologies Ireland Limited in Cork, Ireland, is seeking an experienced ASIC engineer to define, model, and design IP/SoC blocks for high-performance products. You will verify, validate, and document ASIC development and collaborate with cross-functional teams to meet system requirements.

The role emphasizes timing closure, library characterization, and flow automation using Python, TCL, and Spice sign-off tools. A strong background in analog/digital design is required.

Qualifications

• Minimum qualifications: Bachelor’s or higher in science/engineering with relevant ASIC experience.
• Master’s or PhD preferred with 1–3+ years of related work in ASIC design/verification.

Responsibilities

• Define, model, and design IP/SoC blocks (digital/analog).
• Verify, validate, and document ASIC development.
• Collaborate with software/hardware teams to meet system requirements.

Skills

Timing sign-off

Python scripting

Spice extraction

P&R/STA

Automation flows

Education

Master's degree in EEE / Computer Engineering

Bachelor's degree in EEE / Computer Engineering / CS

PhD in related field

Tools

RTL to GDS Flow

Virtuoso

Job description

QT Technologies Ireland Limited in Cork, Ireland, is seeking an experienced ASIC engineer to define, model, and design IP/SoC blocks for high-performance products. You will verify, validate, and document ASIC development and collaborate with cross-functional teams to meet system requirements.

The role emphasizes timing closure, library characterization, and flow automation using Python, TCL, and Spice sign-off tools. A strong background in analog/digital design is required.