STA Design Engineer - ASIC / Low Power

European Tech Recruit; Ireland; On-site; EUR 85,000 - 110,000; Full time

Job summary

European Tech Recruit partners with a global semiconductor leader to hire an STA Design Engineer for Cork, Ireland, responsible for complex timing signoff and closure on next‑gen ASICs.

The role requires 4+ years in STA, proficiency with PrimeTime/Tempus, ECO tools, and strong Python/TCL/Perl scripting to optimize PPA across RTL–GDS flows.

Qualifications

• 4+ years of experience in Static Timing Analysis.
• Proficient with STA tools like PrimeTime/Tempus for hierarchical analysis in large SoCs.
• Experience with ECO tools for timing closure (e.g., Tweaker, PrimeClosure, PTECO, Tempus ECO).
• Strong scripting skills in Python, TCL or Perl for automation.
• Knowledge of RTL-to-GDS flow and ASIC design flow.

Responsibilities

• Perform Static Timing Analysis (STA) and drive timing closure for complex cores and full-chip SOCs.
• Evaluate block-level and top-level timing on gate-level PNR netlists.
• Provide feedback to RTL, Synthesis, and Physical Design teams to improve PPA.
• Create and execute Timing ECOs to resolve critical timing violations.
• Develop automation scripts (Python, TCL, or Perl) for timing/power data mining and processing.

Skills

STA expertise

Automation scripting

ASIC/SoC design knowledge

Tools

PrimeTime

PrimeShield

Tempus

Tweaker

PrimeClosure

PTECO

Tempus ECO

Job description

We are partnered with a global leader in semiconductors and wireless technology focused on developing high-performance, low-power ASIC solutions for advanced cores and SOCs (System-on-Chips). The team are looking to hire an STA Engineer to take responsibility for conducting complex timing signoff activities and drive closure for next-generation products.

This is a permanent working opportunity based in Cork, Ireland.

Key responsibilities for this STA Design Engineer position:

• Perform Static Timing Analysis (STA) and drive timing closure for complex cores and full-chip SOCs (e.g., in the Snapdragon family).
• Evaluate block-level and top-level timing on gate-level PNR netlists.
• Provide critical feedback to the RTL, Synthesis, and Physical Design teams to improve Power, Performance, and Area (PPA).
• Create and execute Timing Engineering Change Orders (ECOs) to resolve critical timing violations.
• Enhance techniques and methodologies for timing closure and STA flow accuracy to reduce turnaround time (TAT).
• Develop automation scripts (Python, TCL, or Perl) for timing/power data mining and processing.

Key requirements:

• 4+ years of related work experience in Static Timing Analysis.
• Expert proficiency in STA tools such as PrimeTime, PrimeShield, or Tempus for hierarchical analysis in large SoCs.
• Hands-on experience with ECO tools (e.g., Tweaker, PrimeClosure, PTECO, Tempus ECO) for timing closure.
• Highly proficient in automation scripting using Python, TCL, or Perl.
• Strong knowledge of the complete ASIC design flow (RTL-to-GDS).

Keywords: STA Design Engineer / Static Timing Analysis / STA / Timing Closure / ASIC Design / SOC / PrimeTime / Tempus / Timing ECO / PPA Optimization / Gate-Level Netlist / Python / TCL / Physical Design / RTL / Synthesis / Semiconductor / High-Performance Cores