Senior Ethernet PHY Architect – Multi-Gig ASIC

Microchip Technology Inc.; Cork; On-site; EUR 90,000 - 130,000; Full time

Job summary

Microchip Technology Inc. in Cork, Ireland, is seeking a Senior Ethernet PHY designer to join the Networking and Connectivity Solutions unit. You will drive architecture and RTL design for high‑speed digital blocks in multi‑gig PHY products, collaborating across global teams to ensure silicon bring‑up.

The role emphasizes verification, pre‑Silicon FPGA emulation, and mentoring junior engineers, with travel up to 25% as needed.

Qualifications

• Bachelor's degree in science/engineering or related field.
• 10+ years of experience in digital ASIC design.
• Experience with RTL coding using Verilog, SystemVerilog or VHDL.
• Strong knowledge of high-speed, asynchronous and low-power circuit design.
• Familiar with automotive/industrial Ethernet standards (802.3bp, 802.3ch, 802.3cg).
• Experience working with global teams and Verilog/SystemVerilog verification.

Responsibilities

• Architecture and development of digital blocks in digital ASIC products.
• Develop RTL code for digital blocks in serial communication PHY layers.
• Perform functional verification and bit-matching with system model.
• Pre-Silicon FPGA design emulation.
• Collaborate with system architects, analog/mixed-signal designers, and verification teams.
• Interface with validation, firmware, and PTE teams to support silicon bring-up.
• Drive design reviews, documentation and technical mentorship to junior engineers.

Skills

Verilog

SystemVerilog

VHDL

RTL coding

High-speed design

Digital ASIC design

Cross-functional teamwork

Automotive Ethernet standards

Education

Bachelor's degree in science/engineering

Job description

Microchip Technology Inc. in Cork, Ireland, is seeking a Senior Ethernet PHY designer to join the Networking and Connectivity Solutions unit. You will drive architecture and RTL design for high‑speed digital blocks in multi‑gig PHY products, collaborating across global teams to ensure silicon bring‑up.

The role emphasizes verification, pre‑Silicon FPGA emulation, and mentoring junior engineers, with travel up to 25% as needed.