Senior Mixed-Signal IP Design Engineer (Low-Power)

QUALCOMM, Inc.; Cork; On-site; EUR 90,000 - 140,000; Full time

Benefits offered by this job

Salary + bonus

Employee stock plan

Relocation support

Education assistance

Health & life insurance

Pension matching

Wellbeing subsidies

Employee clubs

Job summary

QT Technologies Ireland Limited in Cork, Ireland, is seeking an experienced digital design engineer to help design the next generation of high-performance, low-power mixed-signal IPs. You will contribute to architecture, RTL coding, front-end implementation, and collaboration with DV/PD teams for verification and physical implementation.

The role requires a master's degree in a related field and 5+ years of ASIC digital design experience, with strong proficiency in front-end tools and scripting

Qualifications

• Master's degree in electrical engineering, computer engineering, or related field
• 5+ years of experience in ASIC digital design, including micro-architecture and RTL design
• Experience with front-end ASIC tools (Design Compiler, Fusion Compiler, Modelsim, VCS, Spyglass, and Primetime)

Responsibilities

• Architecture, design, and implementation of digital sections of mixed-signal IPs
• Run full suite of ASIC design tools to validate and implement the design
• Collaborate with DV and PD teams for verification and physical implementation
• Create design specifications and documentation
• Work with testing team for silicon bring-up and debug
• Contribute to power, performance, and area optimization

Skills

ASIC digital design

RTL design

micro-architecture

DSP concepts

Education

Master's degree in Electrical Engineering or Computer Engineering

Bachelor's degree in Science, Engineering, or related field

PhD in Science, Engineering, or related field

Tools

Design Compiler

Fusion Compiler

Modelsim

VCS

Spyglass

Primetime

Job description

QT Technologies Ireland Limited in Cork, Ireland, is seeking an experienced digital design engineer to help design the next generation of high-performance, low-power mixed-signal IPs. You will contribute to architecture, RTL coding, front-end implementation, and collaboration with DV/PD teams for verification and physical implementation.

The role requires a master's degree in a related field and 5+ years of ASIC digital design experience, with strong proficiency in front-end tools and scripting