Principal Engineer - Digital Design

Microchip Technology Inc.; Cork; On-site; EUR 90,000 - 130,000; Full time

Job summary

Microchip Technology Inc. in Cork is building a world-class R&D group focusing on Analog, Digital and Communication system design.

We seek Senior Ethernet PHY designers to drive development of multi-gig T1 PHY products, collaborating with global teams and mentoring junior engineers.

Qualifications

• Bachelor’s degree in science, engineering, or a related field.
• 10+ years of experience in digital ASIC design.
• Proficient RTL coding with Verilog, SystemVerilog or VHDL.
• Strong knowledge of high-speed, asynchronous, and low-power circuit design.
• Experience with automotive/industrial Ethernet standards is highly desirable.
• Experience working with global teams.

Responsibilities

• Architecture and development of digital blocks in digital ASIC products.
• Develop RTL code for the digital blocks in serial communication PHY layers.
• Perform functional verification and bit-matching with the system-model.
• Pre-silicon FPGA design emulation.
• Collaborate with system architects, analog/mixed-signal designers, and verification teams.
• Interface with validation, firmware, and PTE teams to support silicon bring-up activities.
• Drive design reviews, documentation and provide technical mentorship to junior engineers.

Skills

Digital ASIC design

RTL coding (Verilog,SystemVerilog,VHDL

High-speed, asynchronous, low-power

Digital IC development flow

Verilog/SystemVerilog

Automotive Ethernet standards

Industrial Ethernet knowledge

Mixed-signal design

DSP algorithms knowledge

Experience with global teams

Education

Bachelor’s degree in science, engineering, or related field

Job description

The Networking and Connectivity Solutions (NCS) BU of Microchip is building a highly skilled R&D group in Cork focusing on Analog, Digital and Communication system design areas.

The NCS team in Cork is seeking Senior Ethernet PHY designers to join our world‑class team and drive the development of cutting‑edge multi‑gig T1 PHY products.

Responsibilities

• Architecture and development of digital blocks in digital ASIC products.
• Develop RTL code for the digital blocks in serial communication PHY layers.
• Perform functional verification and bit‑matching with the system‑model.
• Pre‑silicon FPGA design emulation.
• Collaborate with system architects, analog/mixed‑signal designers, and verification teams.
• Interface with validation, firmware, and PTE teams to support silicon bring‑up activities.
• Drive design reviews, documentation and provide technical mentorship to junior engineers.

Qualifications

• Bachelor’s degree in science, engineering, or related field.
• 10+ years of experience in digital ASIC design.
• Experience in RTL coding with Verilog, SystemVerilog or VHDL.
• Strong knowledge of high‑speed, asynchronous and low‑power circuit design.
• Strong knowledge of digital IC development flow.
• Experience working with global teams.
• Familiarity with function verification using Verilog/System‑Verilog.
• Experience with automotive and industrial Ethernet standards (e.g., 802.3bp, 802.3ch, 802.3cg) is highly desirable.
• Experience in mixed‑signal designs is a plus.
• Knowledge of DSP algorithms and communication systems is a plus.

Travel requirement: 0%–25%.