Senior Ethernet PHY ASIC Design Engineer

FHLB Des Moines; Cork; On-site; EUR 120,000 - 180,000; Full time

Job summary

Microchip Technology Inc. in Cork is building a world-class R&D team focused on Analog, Digital and Communication system design. The Senior Ethernet PHY Designer will contribute to multi-gig T1 PHY products, tackling RTL design, verification, synthesis, and pre-silicon FPGA work.

You will mentor junior engineers and collaborate across engineering disciplines, with travel up to 25%. The role demands a proactive, cross-functional mindset and a track record of delivering high-performance networking

Qualifications

• Bachelor’s degree in science, engineering, or related field.
• 10+ years of experience in digital ASIC design.
• Proficiency in Verilog, SystemVerilog, or VHDL.
• Knowledge of high-speed, low-power design.
• Experience with automotive/industrial Ethernet standards is desirable.

Responsibilities

• Architecture and development of digital blocks in digital ASIC products.
• Develop RTL code for the digital blocks in serial communication PHY layers.
• Perform functional verification and bit-matching with the system-model.
• Pre-Silicon FPGA design emulation.
• Collaborate with system architects, analog/mixed-signal designers, and verification teams.
• Interface with validation, firmware, and PTE teams to support silicon bring-up activities.
• Drive design reviews, documentation and provide technical mentorship to junior engineers.

Skills

Digital ASIC design

RTL coding

Verilog/SystemVerilog

VHDL

High-speed design

Automotive Ethernet knowledge

Team collaboration

Education

Bachelor’s degree in science, engineering, or related field

Job description

Microchip Technology Inc. in Cork is building a world-class R&D team focused on Analog, Digital and Communication system design. The Senior Ethernet PHY Designer will contribute to multi-gig T1 PHY products, tackling RTL design, verification, synthesis, and pre-silicon FPGA work.

You will mentor junior engineers and collaborate across engineering disciplines, with travel up to 25%. The role demands a proactive, cross-functional mindset and a track record of delivering high-performance networking