Technical Staff Digital Design Engineer

Microchip Technology Inc.; Cork; On-site; EUR 90,000 - 130,000; Full time

Job summary

Microchip Technology Inc. in Cork, Ireland, is seeking a Senior Ethernet PHY designer to join the Networking and Connectivity Solutions unit. You will drive architecture and RTL design for high‑speed digital blocks in multi‑gig PHY products, collaborating across global teams to ensure silicon bring‑up.

The role emphasizes verification, pre‑Silicon FPGA emulation, and mentoring junior engineers, with travel up to 25% as needed.

Qualifications

• Bachelor's degree in science/engineering or related field.
• 10+ years of experience in digital ASIC design.
• Experience with RTL coding using Verilog, SystemVerilog or VHDL.
• Strong knowledge of high-speed, asynchronous and low-power circuit design.
• Familiar with automotive/industrial Ethernet standards (802.3bp, 802.3ch, 802.3cg).
• Experience working with global teams and Verilog/SystemVerilog verification.

Responsibilities

• Architecture and development of digital blocks in digital ASIC products.
• Develop RTL code for digital blocks in serial communication PHY layers.
• Perform functional verification and bit-matching with system model.
• Pre-Silicon FPGA design emulation.
• Collaborate with system architects, analog/mixed-signal designers, and verification teams.
• Interface with validation, firmware, and PTE teams to support silicon bring-up.
• Drive design reviews, documentation and technical mentorship to junior engineers.

Skills

Verilog

SystemVerilog

VHDL

RTL coding

High-speed design

Digital ASIC design

Cross-functional teamwork

Automotive Ethernet standards

Education

Bachelor's degree in science/engineering

Job description

Job Description

The Networking and Connectivity Solutions (NCS) BU of Microchip is building a highly skilled R&D group in Cork focusing on Analog, Digital and Communication system design areas. NCS develops networking ICs and software for a broad range of applications ranging from 10 Mbps to 12.5 Gbps speed grades targeting automotive and industrial markets. The NCS team in Cork is seeking Senior Ethernet PHY designers to join our world‑class team and drive the development of cutting‑edge multi‑gig T1 PHY products.

The role will include working in the areas of RTL design, design verification, synthesis, STA, and Test using an industry‑leading ASIC design flow. Candidate will also be responsible for training and mentoring junior engineers to grow the team’s capability. This position requires a proactive and motivated candidate with a proven record of success in a cross‑functional and cross‑site team environment.

What’s Attractive About This Opportunity

This position will expose you to the challenging world of embedded controller design in automotive information and serial communication systems. You will play a key role in the architecture, design, and verification of high‑performance multi‑gigabit T1 Ethernet PHYs.

Key Job Responsibilities / Duties Include

• Architecture and development of digital blocks in digital ASIC products.
• Develop RTL code for the digital blocks in serial communication PHY layers.
• Perform functional verification and bit‑matching with the system‑model.
• Pre‑Silicon FPGA design emulation.
• Collaborate with system architects, analog/mixed‑signal designers, and verification teams.
• Interface with validation, firmware, and PTE teams to support silicon bring‑up activities.
• Drive design reviews, documentation and provide technical mentorship to junior engineers.

Requirements / Qualifications

Qualifications and Experience

• Bachelor’s degree in science, engineering, or related field.
• 10+ years of experience in digital ASIC design.
• Experience in RTL coding with Verilog, System Verilog or VHDL.
• Strong knowledge in high speed, asynchronous and low power circuit design.
• Strong knowledge of digital IC development flow.
• Working with global team experience.
• Familiar with function verification with Verilog/System‑Verilog.
• Experience with automotive and industrial Ethernet standards (e.g., 802.3bp, 802.3ch, 802.3cg) is highly desirable.
• Experience in mixed‑signal designs is a plus.
• Knowledge of DSP algorithms and communication systems is a plus.

Travel Time: 0% - 25%