Senior ASIC Verification Lead for DDR/PCIe IP

Synopsys, Inc.; Dublin; Hybrid; EUR 80,000 - 110,000; Full time

Job summary

Synopsys, Inc. is seeking an experienced ASIC Digital Verification Engineer to design and implement verification environments for Interface IP protocols and to drive coverage closure.

You will collaborate with design teams to identify and fix issues, develop VIP and testbenches, and mentor junior engineers to uphold high standards of quality. You should have deep expertise in SystemVerilog/UVM and be comfortable validating DDR, PCIe, CXL, and Ethernet interfaces across complex ASIC designs.

Qualifications

• Extensive experience in ASIC digital verification.
• Proficient with SystemVerilog and UVM.
• Experience validating Interface IP protocols such as DDR, PCIe, CXL, Ethernet.
• Strong problem-solving and communication skills.
• Ability to mentor and lead junior engineers.

Responsibilities

• Design and implement verification environments for Interface IP protocols.
• Create and execute test plans to verify complex ASIC designs.
• Develop and maintain verification IP and testbenches using SystemVerilog and UVM.
• Collaborate with design and architecture teams to fix bugs.
• Perform functional coverage analysis and drive coverage closure.
• Mentor and guide junior verification engineers in best practices.

Skills

SystemVerilog

UVM

ASIC verification

Debugging

Mentoring

Tools

VCS

ModelSim

Job description

Synopsys, Inc. is seeking an experienced ASIC Digital Verification Engineer to design and implement verification environments for Interface IP protocols and to drive coverage closure.

You will collaborate with design teams to identify and fix issues, develop VIP and testbenches, and mentor junior engineers to uphold high standards of quality. You should have deep expertise in SystemVerilog/UVM and be comfortable validating DDR, PCIe, CXL, and Ethernet interfaces across complex ASIC designs.