Senior ASIC Verification Engineer – RTL/SoC & Protocols

SVENTL ASIA PACIFIC PTE. LTD.; Dublin; On-site; EUR 60,000 - 100,000; Full time

Job summary

SVENTL ASIA PACIFIC PTE. LTD. in Ireland seeks an experienced ASIC verification engineer to help build robust verification environments for IP and SoC validation. You will drive test development, coverage analysis, and regression planning using SystemVerilog, UVM, and related methodologies.

Responsibilities include running simulations, debugging RTL issues, and ensuring effective verification across blocks and full chips, with knowledge of PCIe/UART/Ethernet protocols and MAC/Serdes familiarity.

Qualifications

• 3-9+ years of experience in ASIC verification and methodologies.
• Strong knowledge of SystemVerilog and UVM methodologies.
• Solid understanding of RTL concepts and bus protocols.

Responsibilities

• Develop verification environment and tests to perform Functional (RTL) testing at IP level and SoC Level
• Develop IP level/SoC level test plans based on the design/architectural specs.
• Coverage Analysis and Coding
• Run simulations & regressions, debug test failures to identify test case issues & RTL design issues
• Define and develop block/full chip level verification environment and its components

Skills

ASIC Verification

SystemVerilog

UVM Methodologies

RTL concepts

AHB/AXI protocol

PCIe/USB/Ethernet

MAC/Serdes

Perl

TCL

Communication skills

Tools

Perl

TCL

Job description

SVENTL ASIA PACIFIC PTE. LTD. in Ireland seeks an experienced ASIC verification engineer to help build robust verification environments for IP and SoC validation. You will drive test development, coverage analysis, and regression planning using SystemVerilog, UVM, and related methodologies.

Responsibilities include running simulations, debugging RTL issues, and ensuring effective verification across blocks and full chips, with knowledge of PCIe/UART/Ethernet protocols and MAC/Serdes familiarity.