Senior Analog/Mixed-Signal PLL Design Engineer

MaC VC; Cork; On-site; EUR 90,000 - 120,000; Full time

Benefits offered by this job

Salary + bonus

Maternity/Paternity Leave

Employee stock purchase scheme

Pension matching

Job summary

QT Technologies Ireland Limited in Cork, Ireland, is seeking experienced analog/mixed-signal design engineers to contribute to high-speed clocking IP for SoC and PHY integration. The role emphasizes low-power, low-voltage designs in nanometer CMOS processes, including PLL/DLL/FLL blocks and close collaboration with layout teams for optimal analog layouts.

You will work on transistor-level circuit implementations with Masters/PhD credentials, and engage in architecture analysis, IP delivery, and

Qualifications

• Master’s or Ph.D. in Science, Engineering, or related field.
• 5+ years transistor-level analog mixed-signal design experience.
• Experience with SPICE simulators and schematic capture tools.
• Experience in designing op-amps, bandgaps, differential amplifiers, VCO, PLL, DLL, FLL.
• Full-custom analog layout, layout extraction, verification and sign-off.
• Strong communication and teamwork in a high‑performance environment.

Responsibilities

• Architecture, design, and development of analog/mixed signal hard macros for high‑speed clocking IP.
• Perform custom circuit design in latest process technologies.
• Participate in internal customer requirements discussions.
• Create design specifications.
• Create behavioral models in Verilog.
• Set up, run and analyse circuit simulations.
• QA procedures on developed hard macros.
• Deliver hard macros and support integration and testing.
• Perform silicon characterization and write verification reports.

Skills

Analog design

Mixed-signal design

High-speed design

Scripting

Education

Master's or PhD in Science/Engineering

Bachelor's degree in Science/Engineering

Tools

SPICE simulators

Schematic capture tools

Job description

QT Technologies Ireland Limited in Cork, Ireland, is seeking experienced analog/mixed-signal design engineers to contribute to high-speed clocking IP for SoC and PHY integration. The role emphasizes low-power, low-voltage designs in nanometer CMOS processes, including PLL/DLL/FLL blocks and close collaboration with layout teams for optimal analog layouts.

You will work on transistor-level circuit implementations with Masters/PhD credentials, and engage in architecture analysis, IP delivery, and