Senior Analog/Mixed-Signal IP DDR Design Engineer

MaC VC; Cork; On-site; EUR 85,000 - 120,000; Full time

Benefits offered by this job

Salary and bonuses

Relocation support

Pension scheme

Education assistance

Insurance

Job summary

QT Technologies Ireland Limited, within Qualcomm's Analog Mixed‑Signal IP team, seeks skilled analog/mixed-signal designers to work on Rx/Tx IO blocks, DLL, clocking and high-frequency circuits for DDR and chip‑to‑chip PHY, in Cork.

You will contribute to architecture analysis, pre‑silicon verification, and post‑silicon bringup while collaborating with mask layout and physical design teams at leading-edge process nodes.

Qualifications

• Bachelor's degree in Science, Engineering, or related field with advanced degree preferred.
• 3+ years ASIC design, verification, or related work experience.
• Experience in high-speed analog/mixed-signal design and SPICE/schematic tools.

Responsibilities

• Architecture, design and development of high-speed mixed-signal circuits for LPDDR5, LPDDR6 and next-generation LPDDR systems
• Custom blocks include high-speed Rx/Tx, clock distribution, clocking elements (DLL/PLL), references blocks
• Circuit design for next-generation chip-to-chip architectures
• Custom schematic capture, SPICE analysis and exhaustive pre-silicon validation
• Post-silicon bringup support and system enablement
• Collaborate with Analog Mask Layout and Physical Design teams to deliver IP on latest nodes
• Power Delivery and Signal and Power integrity

Skills

Analog/mixed-signal design

SPICE simulations

Schematic capture

Signal integrity

Communication skills

Education

Master's or Ph.D. in Science/Engineering

Bachelor's degree in Science/Engineering

Tools

SPICE

Schematic capture tools

Job description

QT Technologies Ireland Limited, within Qualcomm's Analog Mixed‑Signal IP team, seeks skilled analog/mixed-signal designers to work on Rx/Tx IO blocks, DLL, clocking and high-frequency circuits for DDR and chip‑to‑chip PHY, in Cork.

You will contribute to architecture analysis, pre‑silicon verification, and post‑silicon bringup while collaborating with mask layout and physical design teams at leading-edge process nodes.