Senior Analog/Mixed-Signal DDR IP Architect

Qualcomm; Cork; On-site; EUR 120,000 - 155,000; Full time

Benefits offered by this job

Stock purchase

Matching pension

Education aid

Relocation support

Insurance

Wellbeing programs

Bike scheme

Employee clubs

Job summary

QT Technologies Ireland Limited is seeking talented analog/mixed-signal designers to develop high-speed circuits for LPDDR5/LPDDR6 and future DDR systems. You will work on Rx/Tx blocks, DLL/PLL timing, and reference/band-gap circuits, contributing to RTL-free design and IP validation.

Experience with SPICE/schematic tools is required, and the role involves collaboration with layout and physical design teams on cutting-edge 2nm and beyond technologies.

Qualifications

• Master’s or Ph.D. in Science, Engineering, or related field.
• 3+ years ASIC design, verification, or related work experience.
• Experience with high-speed DDR/SerDes or IO blocks is preferred.

Responsibilities

• Architecture, design and development of high-speed mixed-signal circuits for LPDDR5/LPDDR6 and next-gen LPDDR systems.
• Designs include Rx/Tx, clock distribution, DLL/PLL, band-gap references.
• Circuit design for chip-to-chip architectures and pre-silicon validation.
• Post-silicon bringup support and system enablement.
• Collaborate with Analog Mask Layout and Physical Design teams for latest nodes.
• Address Power Delivery and SI/PI concerns.

Skills

Analog mixed-signal design

SPICE simulators

Op-amps/Differential amplifiers

PLL/DLL/VCO

DDR/SerDes IO blocks

Signal integrity

GenAI scripting

Education

Master's/PhD in Science/Engineering

Bachelor's degree in Science/Engineering

Tools

SPICE

Schematic capture tools

Job description

QT Technologies Ireland Limited is seeking talented analog/mixed-signal designers to develop high-speed circuits for LPDDR5/LPDDR6 and future DDR systems. You will work on Rx/Tx blocks, DLL/PLL timing, and reference/band-gap circuits, contributing to RTL-free design and IP validation.

Experience with SPICE/schematic tools is required, and the role involves collaboration with layout and physical design teams on cutting-edge 2nm and beyond technologies.