RTL Design & IP Release Engineer – Verilog / Foundation IP / ClearCase / Python

European Tech Recruit; Cork; On-site; EUR 65,000 - 95,000; Full time

Job summary

European Tech Recruit partners with a technology organisation to deliver Foundation IP and IP release support. The role focuses on RTL design updates, quality assurance, configuration management, and IP release activities across a global engineering environment.

The engineer will combine RTL design changes with structured release management and automation using Python, collaborating with design, verification, integration, and programme teams to meet milestones and release deadlines.

Qualifications

• Experience with RTL design and Verilog.
• Experience supporting IP development and release activities.
• Experience with ClearCase-based release processes and QA checks.

Responsibilities

• Implement and validate RTL design changes using Verilog.
• Support Foundation IP development and release activities.
• Manage ClearCase-based IP release processes.
• Perform QA checks on Foundation IP deliverables.
• Maintain configuration management and release documentation.
• Improve IP release workflows through Python scripting and automation.

Skills

RTL design

Verilog

Foundation IP

Python scripting

QA

IP release

Configuration management

Tools

ClearCase

Job description

RTL Design & IP Release Engineer – Verilog / Foundation IP / ClearCase / Python

We are currently partnered with a technology organisation developing and delivering Foundation IP, with an opportunity for an RTL Design & IP Release Engineer to support RTL development, quality assurance, configuration management, and IP release activities across a global engineering environment.

The role combines RTL design updates with structured release management and process automation, working closely with design, verification, integration, and programme teams to deliver high-quality IP releases and maintain project milestones and release deadlines.

Key responsibilities

• Implement and validate RTL design changes using Verilog
• Support Foundation IP development and release activities
• Manage ClearCase-based IP release processes
• Perform quality assurance checks on Foundation IP deliverables
• Maintain configuration management and release documentation
• Improve IP release workflows through Python scripting and automation
• Collaborate closely with design, verification, integration, and programme teams

Key requirements

• Experience with RTL design and Verilog
• Experience supporting IP development and release activities
• Experience with ClearCase-based release processes
• Experience performing QA checks for IP deliverables
• Experience with configuration management and release documentation
• Experience with Python scripting and automation

Keywords

RTL Design / RTL Engineer / RTL Design Engineer / IP Release Engineer / IP Design / IP Release / Foundation IP / Verilog / RTL Verilog / Hardware Design / Digital Design / IP Development / IP Delivery / Release Management / IP Release Management / ClearCase / Configuration Management / Release Processes / Release Workflows / Quality Assurance / QA / IP QA / Release QA / Python / Python Scripting / Automation / Process Automation / Design Engineering / Design Verification / IP Integration / Engineering Integration / Programme Coordination / Cross-Functional Collaboration / Global Engineering / Release Documentation / Configuration Management / Issue Resolution

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