RTL Design & IP Release Engineer

European Tech Recruit; Cork; On-site; EUR 50,000 - 70,000; Full time

Job summary

Unknown company in Cork, Ireland is seeking an RTL Design & IP Release Engineer on a 6 month contract to support Foundation IP development, release activities, and QA checks within a large-scale semiconductor environment.

You will work across RTL design, IP integration, release management, configuration management, and automation, developing scripts in Python to improve engineering workflows and coordinate deliverables with distributed teams.

Qualifications

• Experience in RTL design using Verilog or SystemVerilog.
• Background in Foundation IP development, integration, or release.
• Experience implementing and validating RTL design changes and IP releases.

Responsibilities

• Implement and validate RTL design changes and fixes.
• Support release of Foundation IP deliverables and QA checks.
• Coordinate with design, verification and integration teams to meet milestones.

Skills

RTL design

Verilog/SystemVerilog

Foundation IP release

IP release & delivery

Configuration management

Python scripting

Automation

Cross-functional collaboration

Issue resolution

Documentation

Tools

Git

Jenkins

Job description

RTL Design Foundation IP Release Engineering Python

6 Month Contract in Cork, Ireland.

A leading global semiconductor company is looking for an RTL Design & IP Release Engineer to support Foundation IP development, quality assurance, and release activities.

This is an opportunity to work across RTL design, IP integration, release management, configuration management, and automation within a large-scale semiconductor engineering environment.

Successful candidates will implement and validate RTL design changes, support the release of Foundation IP deliverables, and perform quality assurance checks to ensure releases meet engineering and project requirements. You will work closely with design, verification, integration, and programme teams across multiple global sites, helping to resolve issues proactively and keep release milestones on track.

Ideal candidates will have knowledge of:

• RTL design using Verilog and/or SystemVerilog
• Foundation IP development, integration, or release
• Implementing and validating RTL design changes
• IP release and delivery processes
• Configuration management and release management
• RTL quality assurance and validation processes
• Python scripting and automation
• Developing scripts to improve engineering and release workflows
• Working with design, verification, and integration teams
• Troubleshooting and proactively resolving technical and release issues
• Maintaining release documentation and configuration information
• Coordinating engineering deliverables and project milestones
• Working with geographically distributed engineering teams
• Strong communication and cross-functional collaboration

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