RTL Design & IP Release Engineer

Berkley Group; Cork; On-site; EUR 74,000 - 111,000; Full time

Job summary

Berkley Group is seeking an RTL Design & IP Release Engineer on an initial 6 month contract. The role focuses on implementing and validating RTL design changes using Verilog/SystemVerilog, supporting IP release and configuration management.

You'll collaborate with design, verification and programme teams across multiple locations, maintain release documentation, and develop Python scripts to automate workflows.

Qualifications

• Experience with RTL integration and ASIC design.
• Strong knowledge of Verilog/SystemVerilog.
• Proficiency with Linux environments.
• Familiarity with DesignSync or similar tools.
• Knowledge of CDC (Clock Domain Crossing) and Lint.

Responsibilities

• Implement and validate RTL design changes using Verilog/SystemVerilog.
• Support the development, integration and release of Foundation IP.
• Perform QA checks on IP deliverables to meet standards.
• Manage IP release and configuration management processes.
• Collaborate with design, verification, integration and programme teams to meet deadlines.
• Develop and maintain Python and other scripting automation.
• Support day-to-day coordination of release-related issues.

Skills

RTL integration

Verilog/SystemVerilog

Python scripting

AMBA protocols

Linux

CDC

Lint

Release management

Configuration management

Tools

DesignSync

Job description

My client, a leading technology organisation, is on the lookout for a RTL Design & IP Release Engineer on an initial 6 month contract.

The Job:

• Implement and validate RTL design changes using Verilog/SystemVerilog.
• Support the development, integration and release of Foundation IP.
• Perform quality assurance checks on IP deliverables to ensure they meet required standards.
• Support ASIC design and RTL integration activities.
• Manage IP release and configuration management processes.
• Work with design, verification, integration and programme teams to resolve issues and meet release deadlines.
• Collaborate with engineering teams across multiple locations.
• Maintain release documentation and ensure deliverables are accurately managed.
• Identify opportunities to improve release processes and engineering workflows.
• Develop and maintain Python and other scripting automation to improve efficiency.
• Support day-to-day coordination and proactive resolution of technical and release-related issues.

Have you:

• Experience with RTL integration and ASIC design.
• Knowledge of CDC (Clock Domain Crossing) and Lint.
• Strong experience with Verilog/SystemVerilog.
• Understanding of AMBA protocols.
• Experience with scripting, particularly Python or similar languages.
• Experience working in a Linux environment.
• Familiarity with DesignSync or similar configuration/release management tools.
• Strong attention to detail when working with IP deliverables, configuration management and release processes.
• Good communication skills and the ability to collaborate effectively with cross-functional and geographically distributed teams.