Senior Design Verification Engineer

European Tech Recruit; Cork; On-site; EUR 60,000 - 90,000; Full time

Job summary

European Tech Recruit is partnering with a leading technology innovator in Cork, Ireland, to hire an experienced Verification Engineer. You will apply UVM, formal verification, and constrained‑random techniques to verify ASICs and ensure tapeout‑quality sensor algorithms.

Responsibilities include building RTL testbenches, C models, SystemVerilog assertions, Python automation, and regression frameworks. You will collaborate across design, systems and software teams and contribute to documentation

Qualifications

• Bachelor's degree in Science, Engineering, or related field.
• 3+ years in ASIC verification or similar roles.
• Proficiency in UVM and SystemVerilog (including SVAs).
• Experience with constrained-random verification and coverage-driven verification.

Responsibilities

• Apply UVM and formal verification methodologies.
• Develop testbenches and verification components (UVCs, C models, vertical/horizontal envs).
• Perform RTL verification of sensor algorithms for tapeout-quality delivery.
• Create test plans based on design specs; collaborate with design and systems teams.
• Integrate C models within UVM-based verification frameworks.
• Develop SystemVerilog assertions to validate design correctness.
• Debug, verify, and optimize designs to meet reference test vectors.
• Analyze coverage metrics and close gaps with design teams.
• Develop and enhance regression frameworks; debug regression failures with cross‑functional teams.
• Support subsystem integration, including test planning, vector delivery, and debugging.
• Build Python-based automation to improve workflows and efficiency.
• Participate in project reviews and provide technical input.

Skills

Analytical thinking

Team collaboration

Problem solving

Excellent communication

Education

Bachelor's degree in Science/Engineering

Tools

UVM

SystemVerilog

RTL simulation tools

Python

C/C++

Job description

As a leading technology innovator, our client pushes the boundaries of what’s possible to enable next-generation experiences and drive transformation in communication and data processing, helping to build a smarter, more connected future.

They are now seeking an experienced Verification Engineer to join their team!

Key Responsibilities

• Apply industry-leading verification methodologies, including UVM and formal verification
• Develop testbenches and verification components such as UVCs, C models, and reusable vertical and horizontal verification environments
• Perform RTL verification of sensor algorithms to ensure ASIC tapeout-quality delivery
• Create detailed test plans based on design specifications, collaborating closely with design and systems teams
• Integrate C models within UVM-based verification frameworks
• Develop SystemVerilog assertions to validate design correctness
• Debug, verify, and optimize designs, ensuring bit-accurate results against reference test vectors
• Analyze coverage metrics and work with design teams to close coverage gaps
• Develop and enhance regression frameworks and debug regression failures in collaboration with cross‑functional teams
• Support subsystem‑level integration, including test planning, vector delivery, and debugging
• Build Python‑based automation to improve workflows and team efficiency
• Participate in project reviews and provide technical input
• Support software and cross‑functional teams in debugging activities
• Maintain clear and comprehensive technical documentation

Required Qualifications

• Bachelor’s degree in Science, Engineering, or a related field
• 3+ years of experience in ASIC design verification, UVM‑based functional verification, or similar roles
• Strong expertise in constrained‑random verification methodologies and coverage‑driven verification
• Proficiency in UVM and SystemVerilog, including SystemVerilog Assertions
• Experience with RTL simulation tools and debugging verification failures to achieve coverage goals
• Scripting skills in Python, Perl, or shell scripting
• Familiarity with C/C++
• Strong analytical and problem‑solving skills, with the ability to work effectively in a fast‑paced environment
• Excellent written and verbal communication skills
• Strong collaboration skills and a team‑oriented mindset

Preferred Qualifications

• Experience with formal verification tools (e.g., Jasper, VC Formal)
• Exposure to SystemC and MATLAB
• Experience with gate‑level simulation, debug, and power analysis tools

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