RTL Design & IP Release Engineer for Global Releases

GCS Recruitment; Cork; On-site; EUR 70,000 - 110,000; Full time

Job summary

GCS Recruitment Specialists is seeking an experienced RTL Design & IP Release Engineer to support Foundation IP development and release activities through RTL design updates, quality assurance, configuration management, and release execution.

The role focuses on implementing and validating RTL changes, managing IP release processes, ensuring deliverable quality, and driving process improvements via scripting and automation.

Qualifications

• Experience in RTL Integration and ASIC Design.
• Strong Verilog/SystemVerilog knowledge.
• Experience with Linux scripting and automation.
• Familiarity with IP release processes.

Responsibilities

• Support Foundation IP development and release activities, including RTL updates, validation, and release management.
• Implement and verify RTL design changes using Verilog/SystemVerilog methodologies.
• Perform quality assurance checks on Foundation IP deliverables to ensure compliance with release standards.
• Manage configuration control and release workflows using version control and release management tools.
• Develop and maintain automation scripts to improve release efficiency and reduce manual effort.
• Collaborate with design, verification, integration, and program teams to deliver high-quality IP releases.
• Coordinate with global stakeholders to proactively resolve technical and process-related issues.
• Maintain release documentation and ensure project milestones and release deadlines are achieved.

Skills

RTL Integration

ASIC Design

Verilog/SystemVerilog

CDC

Lint analysis

AMBA protocols

Scripting

Linux

DesignSync

Stakeholder management

Tools

DesignSync

Version control

Python scripting

Job description

We are seeking an experienced RTL Design & IP Release Engineer to support Foundation IP development and release activities through RTL design updates, quality assurance, configuration management, and release execution. This role will focus on implementing and validating RTL changes, managing IP release processes, ensuring deliverable quality, and driving process improvements through scripting and automation.

Key Responsibilities

• Support Foundation IP development and release activities, including RTL updates, validation, and release management.
• Implement and verify RTL design changes using Verilog/SystemVerilog methodologies.
• Perform quality assurance checks on Foundation IP deliverables to ensure compliance with release standards.
• Manage configuration control and release workflows using version control and release management tools.
• Develop and maintain automation scripts to improve release efficiency and reduce manual effort.
• Collaborate with design, verification, integration, and program teams to deliver high-quality IP releases.
• Coordinate with global stakeholders to proactively resolve technical and process-related issues.
• Maintain release documentation and ensure project milestones and release deadlines are achieved.

Required Skills & Experience

• Experience in RTL Integration and ASIC Design.
• Strong knowledge of Verilog and SystemVerilog.
• Hands-on experience with Clock Domain Crossing (CDC) and Lint analysis.
• Understanding of AMBA protocols and integration methodologies.
• Experience with scripting and automation in Linux environments.
• Knowledge of DesignSync or similar configuration management tools.
• Strong problem-solving skills and the ability to work effectively in cross-functional engineering teams.
• Excellent communication and stakeholder management skills within global development environments.

Desirable

• Experience with IP release flows and release management processes.
• Exposure to Physical Verification methodologies.
• Proficiency in Python scripting for automation and process improvement.
• Experience supporting large-scale semiconductor or SoC development programs.
• Knowledge of configuration management and software development lifecycle best practices.

Ideal Candidate

A detail-oriented RTL Design & IP Release Engineer with a strong background in ASIC design and RTL integration. You will be comfortable working across globally distributed teams, driving technical coordination, automating manual processes, and ensuring the successful delivery of high-quality IP releases. A proactive mindset, excellent communication skills, and a passion for continuous process improvement will be key to success in this role.

GCS is acting as an Employment Business in relation to this vacancy.