Staff Mixed-Signal Digital Design Engineer

European Tech Recruit

Cork

On-site

EUR 80,000 - 110,000

Full time

2 days ago
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Job summary

European Tech Recruit is seeking a Staff Mixed-Signal Digital Design Engineer in Cork. You will help develop high-performance, low-power mixed-signal IP and take digital designs from microarchitecture to RTL and physical implementation.

You will collaborate with architecture, verification, and hardware teams to optimise PPA and ensure successful silicon bring-up, while contributing to design specs and technical docs.

Qualifications

  • Degree in electrical or computer engineering or related field.
  • ≥5 years ASIC digital design experience including microarchitecture and RTL.
  • Strong experience with Verilog/SystemVerilog and RTL verification.

Responsibilities

  • Architect, design, and implement digital components of mixed-signal IP (SerDes, DDR PHY, PLL/DLL/FLL).
  • Define microarchitectures and develop RTL for complex ASIC designs.
  • Apply digital design and PPA optimization techniques to enhance power, performance, and area.
  • Use front-end ASIC tools: lint, CDC, DFT, synthesis, formal verification, STA.
  • Collaborate with verification, physical design, and test teams to validate functionality.
  • Produce design specifications and technical documentation.
  • Support silicon bring-up, testing, and debugging with the team.

Skills

Digital design
ASIC design
RTL development

Education

Electrical Engineering or Computer Engineering degree

Tools

Verilog/SystemVerilog
Design Compiler
Fusion Compiler
ModelSim
VCS
SpyGlass
PrimeTime

Job description

Staff Mixed-Signal Digital Design Engineer - Cork - (Relocation offered for EU-based Candidates)

We're looking for an experienced digital design engineer to help develop the next generation of high-performance, low-power mixed-signal IP for advanced semiconductor products.

This is an opportunity to join a specialist engineering team working across architecture, ASIC design, digital signal processing and hardware implementation. You'll play a key role in taking digital designs from microarchitecture definition through RTL implementation, validation and physical implementation, collaborating with engineers across multiple disciplines.

What you'll be doing

  • Architect, design and implement digital components of mixed-signal IP, including SerDes, DDR PHY, PLL/DLL/FLL, ADC/DAC and sensor-related designs.
  • Define microarchitectures and develop high-quality RTL for complex ASIC designs.
  • Apply digital design, computer architecture and signal-processing techniques to optimise power, performance and area (PPA).
  • Use front-end ASIC design tools and flows, including lint, clock-domain crossing (CDC), design-for-test (DFT), synthesis, formal verification and static timing analysis (STA).
  • Work closely with design verification engineers to define test plans, validate functionality and resolve design issues.
  • Collaborate with physical design engineers to support implementation and achieve design targets.
  • Produce design specifications and technical documentation.
  • Support silicon bring-up, testing and debugging alongside the wider engineering team.

Required Experience

  • A degree in Electrical Engineering, Computer Engineering or a related technical discipline.
  • At least 5 years of relevant ASIC digital design experience, including microarchitecture definition and RTL development.
  • Strong practical experience with Verilog and/or SystemVerilog.
  • Experience with front-end ASIC tools such as Design Compiler, Fusion Compiler, ModelSim, VCS, SpyGlass and PrimeTime.
  • An understanding of ASIC design flows and the interaction between RTL design, verification and physical implementation.
  • Strong communication skills and the ability to collaborate effectively within a technically demanding engineering team.

Desired Experience

  • Low-power digital design and PPA optimisation.
  • Computer architecture, DSP or algorithm development.
  • Scripting with Python or Perl.
  • Hands-on experience designing at least one mixed-signal IP domain, such as:
  • SerDes and high-speed interfaces, including USB, PCIe, MIPI or UFS.
  • DDR PHY and memory interfaces.
  • Timing circuits, including PLL, DLL and FLL.
  • Data converters, including ADC and DAC.
  • Digital components of sensor interfaces.
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