Physical Design Engineer II

SVENTL ASIA PACIFIC PTE. LTD.; Dublin; On-site; EUR 70,000 - 110,000; Full time

Job summary

SVENTL ASIA PACIFIC PTE. LTD. is seeking an experienced EDA engineer in Ireland to contribute to tapeouts from Netlist to GDSII at block, subsystem and full-chip levels.

The role emphasizes high-performance, low-power core design, multi-node experience, and robust timing signoff processes. Responsibilities include floor planning, power planning, IR drop analysis, CTS/clock tree constraints, and TCL scripting to optimize tool usage across STA/ECO cycles.

Qualifications

• Experience with Netlist to GDSII/tapeouts.
• Exposure to 7nm/10nm/14nm/28nm process nodes.
• Timing Signoff in loop through STA and ECO cycles at block/interface.
• Block-level floor planning and power planning expertise.
• IR drop analysis and Crosstalk considerations.

Responsibilities

• Netlist to GDSII at block level, Subsystem level and Full chip.
• Worked on multiple tapeouts on Netlist to GDSII.
• Hierarchical partitioning and budgeting of block-level subsystems.
• Implementation of high performance cores and low power designs.
• Node experience upto 7nm, 10nm, 14nm, 28nm.
• Timing Signoff in loop through STA and ECO cycle at block and at interface.
• Block level floor planning, power planning and IR drop analysis.
• Scan chain reordering / Scan Chain repartitioning
• CTS expertise and clock tree constraints creation for meeting specifications
• MMMC optimization at Block and Sub-System Level
• Timing closure with Crosstalk and AOCV / POCV
• TCL scripting to fundamentally understand tool usage.

Skills

Hierarchical partitioning

Block-level floor planning

Power planning

IR drop analysis

Scan chain optimization

Clock tree constraints

Timing closure

TCL scripting

Tools

Synopsys ICC/ICC2

Cadence Innovus

Job description

Job Description & Requirements

• Netlist to GDSII at block level, Subsystem Level and at Full chip.
• Worked on multiple tapeouts on Netlist to GDSII
• Hierarchical partitioning and budgeting of block-level subsystems.
• Implementation of high performance (HP) cores, low power designs
• Node experience upto 7nm, 10nm, 14nm, 28nm.
• Timing Signoff in loop through STA and ECO cycle at block and at interface.
• Block level floor planning, power planning and IR drop analysis.
• Scan chain reordering / Scan Chain repartitioning
• CTS expertise and clock tree constraints creation for meeting specifications
• MMMC optimization at Block and Sub-System Level
• Timing closure with Crosstalk and AOCV / POCV
• TCL scripting to fundamentally understand tool usage.

MANDATORY EDA SKILLS

• PnR tools such as Synopsys ICC/ICC2 and/or Cadence Innovus