Physical Design Implementation

European Tech Recruit; Cork; On-site; EUR 90,000 - 130,000; Full time

Job summary

European Tech Recruit is seeking a Senior Physical Design Implementation Engineer to join our client’s team in Ireland.

You will own the PD lifecycle from netlist handoff to GDS, including floorplanning, power planning, placement, CTS, routing and optimization, and you will work with advanced-node tools (10nm and below).

A deep understanding of STA, timing-closure strategies, power integrity, and PD verification flows is essential to deliver DRC-clean layouts and high-quality PPA.

Qualifications

• 4+ years of hands-on PD experience.
• Full PD lifecycle knowledge from netlist handoff to GDS.
• Experience on advanced-node tools (10nm and below).
• Solid STA, timing-closure strategies understanding.
• Knowledge of power analysis and power integrity.
• Familiar with Physical Verification flows and DRC-clean layouts.

Skills

Physical Design

PD lifecycle knowledge

Advanced-node tools

STA and timing-closure

Power analysis & PI

Physical Verification & DRC

Tools

Cadence

Synopsys

GDS II

Job description

Senior Physical Design Implementation Engineer

Would you like to work for one of the global semiconductor leaders? Now hiring for a Senior Physical Design Implementation Engineer to join the team.

Key experience needed for the Senior Physical Design Implementation Engineer role:

• 4+ years of hands-on experience working in Physical Design.
• Strong grasp of the full PD lifecycle, from netlist handoff through GDS, including floorplanning, power planning, placement, CTS, routing, and associated optimization.
• Solid background using advanced-node physical design tools (10nm and below) for implementation and signoff.
• Deep understanding of STA concepts, timing-closure strategies, and how timing impacts congestion, routing quality, and power.
• Familiarity with power analysis and power-integrity evaluation techniques.
• Working knowledge of Physical Verification flows and achieving DRC-clean layouts.

Keywords:

ASIC / Physical Design / SoC / RTL / GDS / Place & Route / STA / RTL-to-GDS / IP Design / Digital Design / Cadence / Synopsys / Semiconductor / Timing Closure / PPA Optimization

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