Engineer

eTeam; Cork; On-site; EUR 90,000 - 130,000; Full time

Job summary

eTeam in Cork, Ireland, is seeking a Design Engineer to join the Microcontroller Sub-System IP team and shape cutting-edge digital designs. You will contribute to micro-architecture, RTL development, debugging, and cross-functional collaboration across DFT, Implementation, Verification, Emulation, and Firmware teams.

The role requires 5+ years in ASIC design, familiarity with ARM THUMB or RISC‑V ISAs, and experience with multi-clock and multi-power domains.

Qualifications

• Bachelor's degree in Science, Engineering, or a related field.
• 5+ years of ASIC design experience.
• Experience with ISAs such as ARM THUMB or RISC‑V.
• Experience with multi-clock and multi-power designs.

Responsibilities

• Micro-Architecture: design micro-architecture for digital blocks.
• RTL Development: develop RTL code with multi-clock, high-frequency, low-power considerations.
• Debugging and Post-Silicon Bring‑Up: troubleshoot and support bring‑up activities.
• Documentation: create design documentation for clarity and maintainability.
• Design Optimization: optimize for area, power, and performance.
• Collaborate with DFT, Implementation, Verification, Emulation, and Firmware teams.

Skills

ASIC design

RTL development

Micro-architecture

Multi-clock domain

Multi-power domain

Python/Perl scripting

DFT/Verification basics

ISAs ARM/RISC‑V

Processor/microcontroller design

Documentation

Education

Bachelor's degree

Tools

RTL tools

EDA tools

Job description

Job Location - Two Penrose Dock, Floors 2, 3, 4, Cork, Ireland, T23 YY09

Job Start Date - 7/31/26

Job End Date - 1/29/27

Job Description

About the Role

The Microcontroller Sub-System IP team plays a crucial role in enabling embedded processing solutions across various functions and products. This team deals with security, power management, and other system-on-chip (SoC) functions across multiple business units (IoT, Mobile, Auto, XR, Compute, etc.). If you’re passionate about solving complex problems and want to be part of a diverse, multicultural team, read on!

As a Design Engineer, you’ll play a critical role in shaping cutting‑edge digital designs. Your responsibilities will include:

• Micro-Architecture: Designing micro-architecture for both simple and complex digital blocks.
• RTL Development: Developing RTL (Register Transfer Level) code using industry best practices. This includes handling multi-clock designs, high-frequency requirements, low power, and low latency considerations while ensuring high performance.
• Debugging and Post-Silicon Bring‑Up: Troubleshooting and debugging issues during the development process and supporting post‑silicon bring‑up activities.
• Documentation: Creating comprehensive design documentation to ensure clarity and maintainability.
• Design Optimization: Optimizing designs for key metrics such as area, power, and performance.
• Cross-Functional Collaboration: Collaborating with cross‑functional teams, including DFT (Design for Testability), Implementation, Verification, Emulation, and Firmware teams.

We’re seeking Engineers with the following attributes and experience:

• Positive Attitude: Bring a fun-loving attitude and a passion for inclusively solving problems.
• Education: Bachelor’s degree in Science, Engineering, or a related field.
• Experience: 5+ years of ASIC design experience
• Complex Digital Logic Design: Experience with designing complex digital logic blocks.
• ISA Familiarity: Knowledge of ISAs (Instruction Set Architectures) such as ARM THUMB or RISC‑V.
• Processor/Microcontroller System Design: Understanding of processor or microcontroller system design.
• Multi-Power Domain and Multi-Clock Domain Designs: Experience with designs spanning multiple power domains and clock domains.
• Scripting/Automation Languages: Proficiency in scripting or automation languages like Python or Perl.
• Industry Standard Digital Tools: Familiarity with state-of-the-art industry-standard digital design tools.
• Challenges of Lower Node Technologies: Awareness of challenges faced when working with lower node technologies.