Physical Design Engineer

European Tech Recruit; Dublin; On-site; EUR 90,000 - 120,000; Full time

Job summary

European Tech Recruit seeks a Physical Design Engineer to join a global semiconductor leader. You will work on physical design across the full lifecycle, from netlist handoff through GDS, including floorplanning, power planning, placement, CTS, routing, and optimization.

Deep knowledge of STA, timing-closure strategies, and power integrity is required, along with hands-on experience in advanced-node PD tools (10nm and below). Cadence/Synopsys skills are a plus.

Qualifications

• Hands-on experience in Physical Design and implementation.
• Deep knowledge of the full Physical Design lifecycle from netlist handoff to GDS.
• Experience with floorplanning, power planning, placement, CTS, routing and optimization.
• Proficiency with advanced-node physical design tools (10nm and below).
• Understanding of STA, timing-closure strategies, and their impact on congestion, routing quality, and power.
• Familiarity with power analysis and power-integrity evaluation techniques.
• Experience with Physical Verification flows and achieving DRC-clean layouts.

Responsibilities

• Apply hands-on physical design methods to deliver signoff-ready layouts.
• Troubleshoot timing, congestion, and power issues across the PD flow.
• Collaborate with RTL, analog/migital designers, and verification teams.
• Utilize Cadence/Synopsys tools for place & route and signoff tasks.
• Support DRC/GDS checks and layout quality improvements.

Skills

Physical Design

Implementation

Floorplanning

Power planning

Placement

CTS

Routing

Optimization

Advanced-node tools

STA concepts

Timing closure

Power analysis

Power integrity

Physical Verification

DRC-clean layouts

Cadence

Synopsys

Semiconductor

Tools

Cadence

Synopsys

Job description

Would you like to work for one of the global semiconductor leaders? Now hiring for a Physical Design Engineer to join the team.

Key experience needed for the Physical Design Engineer role:

• Strong experience hands-on experience working in Physical Design and implementation
• deep knowledge of the full Physical Design lifecycle, from netlist handoff through GDS, including floorplanning, power planning, placement, CTS, routing, and associated optimization.
• Solid background using advanced-node physical design tools (10nm and below) for implementation and signoff.
• Deep understanding of STA concepts, timing-closure strategies, and how timing impacts congestion, routing quality, and power.
• Familiarity with power analysis and power-integrity evaluation techniques.
• Working knowledge of Physical Verification flows and achieving DRC-clean layouts.

Keywords: ASIC / Physical Design / SoC / RTL / GDS / Place & Route / STA / RTL-to-GDS / IP Design / Digital Design / Cadence / Synopsys / Semiconductor / Timing Closure / PPA Optimization

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