Physical Design Engineer

SVENTL ASIA PACIFIC PTE. LTD.; Dublin; On-site; EUR 70,000 - 110,000; Full time

Job summary

SVENTL ASIA PACIFIC PTE. LTD. seeks an experienced EDA engineer to drive Netlist-to-GDSII tapeouts across block, subsystem and full-chip levels.

You will perform hierarchical partitioning, floor planning, and power/IR drop analysis while delivering timing-closed designs for 7nm to 28nm nodes. Responsibilities include chaining STA/ECO signoff loops, scan chain optimization, CTS creation, and TCL scripting to automate tool flows.

Qualifications

• Experience with Netlist to GDSII flow for block, subsystem and full-chip tapeouts.
• Hierarchical partitioning and budgeting of block-level subsystems.
• Implementation of high performance cores with low power design techniques.
• Node experience upto 7nm, 10nm, 14nm, 28nm.
• Timing signoff loops through STA and ECO at block/interface levels.
• Block-level floor planning, power planning and IR drop analysis.
• Scan chain reordering / repartitioning.
• CTS expertise and clock tree constraints creation for meeting specs.
• MMMC optimization at Block and Sub-System level.
• Timing closure addressing Crosstalk and AOCV/POCV.
• TCL scripting to understand tool usage.

Responsibilities

• Lead end-to-end netlist-to-GDSII flows for blocks, subsystems and full chip.
• Perform hierarchical partitioning and block-level budgeting to meet timing and area goals.
• Develop high-performance, low-power core implementations.
• Execute multi-node flows across 7nm/10nm/14nm/28nm nodes with signoff readiness.
• Run timing signoff loops (STA/ECO) at block and interface levels.
• Plan floor, power and IR drop strategies at block level.
• Reorder/repartition scan chains to optimize testability and area.
• Create clock tree constraints (CTS) to meet specs and timing.
• Optimize MMMC at block/system level and address crosstalk.

Skills

Tapeouts

Partitioning

Power planning

IR drop analysis

Scan chain

Clock tree

Timing closure

TCL scripting

Tools

Synopsys ICC/ICC2

Cadence Innovus

Job description

Netlist to GDSII at block level, Subsystem Level and at Full chip.

• Worked on multiple tapeouts on Netlist to GDSII
• Hierarchical partitioning and budgeting of block-level subsystems.
• Implementation of high performance (HP) cores, low power designs
• Node experience upto 7nm, 10nm, 14nm, 28nm.
• Timing Signoff in loop through STA and ECO cycle at block and at interface.
• Block level floor planning, power planning and IR drop analysis.
• Scan chain reordering / Scan Chain repartitioning
• CTS expertise and clock tree constraints creation for meeting specifications
• MMMC optimization at Block and Sub-System Level
• Timing closure with Crosstalk and AOCV / POCV
• TCL scripting to fundamentally understand tool usage.

MANDATORY EDA SKILLS

• PnR tools such as Synopsys ICC/ICC2 and/or Cadence Innovus