Digital ASIC Engineer: RTL, Synthesis & Low-Power Design

European Tech Recruit; Ireland; On-site; EUR 70,000 - 95,000; Full time

Job summary

European Tech Recruit is assisting a leading semiconductor company in Ireland to hire a Digital ASIC Engineer. You will contribute to end-to-end design of digital blocks for consumer devices, work with RTL, SystemVerilog, and Python tooling, and help deliver timing-closed netlists for layout.

You’ll collaborate with systems architects and other HW/SW engineers to integrate blocks into larger chip designs, perform synthesis and timing closure, and support low-power design considerations.

Qualifications

• Degree in engineering or science required.
• Solid RTL design and SystemVerilog experience.
• Proficient in scripting (Python/Tcl/Perl) and 2+ years in Digital TRL design.

Responsibilities

• Design and code digital logic blocks for chip integration.
• Verify designs against test benches and fix bugs.
• Handle synthesis and timing closure with standard EDA tools.
• Consider power budgets and contribute to low-power design decisions.
• Write scripts to speed up team processes.
• Collaborate with systems architects and HW/SW engineers to integrate blocks into larger chip designs.

Skills

RTL Design

SystemVerilog

Python scripting

C++/SystemC

Education

Engineering or science degree

Tools

PrimeTime/PTPX

LEC

Synthesis tools

Job description

European Tech Recruit is assisting a leading semiconductor company in Ireland to hire a Digital ASIC Engineer. You will contribute to end-to-end design of digital blocks for consumer devices, work with RTL, SystemVerilog, and Python tooling, and help deliver timing-closed netlists for layout.

You’ll collaborate with systems architects and other HW/SW engineers to integrate blocks into larger chip designs, perform synthesis and timing closure, and support low-power design considerations.