Digital ASIC Design Engineer

European Tech Recruit; Ireland; On-site; EUR 60,000 - 90,000; Full time

Job summary

European Tech Recruit is partnering with a leading semiconductor company in Ireland to hire a Digital ASIC Design Engineer. The role involves designing and coding digital logic blocks for chip integration, verifying with testbenches, and performing synthesis and timing closure to deliver clean netlists for layout.

You will collaborate with systems architects and HW/SW engineers, writing RTL in SystemVerilog and scripting in Python/Tcl/Perl, while contributing to low-power design choices and

Qualifications

• A relevant engineering or science degree.
• Solid RTL Design experience with SystemVerilog and scripting.
• 2+ years of Digital RTL Design experience in a professional setting.

Responsibilities

• Designing and coding digital logic blocks destined for chip integration.
• Verifying designs against test benches and fixing bugs.
• Handling synthesis and timing closure with standard EDA signoff tools.
• Looking at power budgets and shaping low-power design choices.
• Writing scripts/tools (Python) to speed up team processes.
• Collaborating with systems architects and other engineers.

Skills

RTL Design

SystemVerilog

Python

Scripting (Tcl/Perl)

EDA Tools (PrimeTime)

C++/SystemC

DFT/MBIST

Education

Engineering degree

Tools

PrimeTime/PTPX

Synthesis

LEC

DRC/CDC checks

Job description

Digital ASIC Design Engineer

Our client, a well-established semiconductor business supplying chip IP into consumer electronics, is looking to add a Digital ASIC Engineer to their design team. The role sits within a group responsible for custom digital blocks that end up inside phones, wearables, connected vehicles and other everyday hardware.

You'll be involved end-to-end: writing specs, coding and verifying RTL, running synthesis, and handing off clean, timing-closed netlists ready for layout. It's a genuinely collaborative role, you'll be working alongside systems architects and other hardware/software engineers to get digital blocks integrated cleanly into larger chip designs.

Day to day, you'll be:

• Designing and coding digital logic blocks destined for chip integration
• Verifying designs against test benches, chasing down and fixing bugs
• Handling synthesis and timing closure work using standard EDA signoff tools
• Looking at power budgets and helping shape low-power design choices
• Writing scripts/tooling (Python) to speed up team processes
• Working with other engineering functions and supporting release governance

On paper, we'd like to see:

• A relevant engineering or science degree
• Solid RTL Design experinece as well as comfortable in SystemVerilog, plus scripting (Python/Tcl/Perl)
• 2+ years of Digital TRL Design experience in a professional setting
• Solid tooling exposure; synthesis, LEC, PrimeTime/PTPX or similar signoff tools
• Nice to have: ECO experience, DRC/CDC checks, C++/SystemC, DFT/MBIST exposure
• A clear communicator who's happy working at pace in a team setting

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