Design Engineer

European Tech Recruit; Cork; On-site; EUR 120,000 - 180,000; Full time

Job summary

European Tech Recruit is seeking a Staff Microcontroller Subsystem Design Engineer for an Ireland-based role.

You will drive embedded processing solutions across IoT, Mobile, Automotive, XR, and Compute platforms, shaping digital architectures from RTL to silicon bring-up.

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
• 5+ years of hands-on ASIC/SoC digital design experience.
• Deep experience in RTL development using SystemVerilog or Verilog.
• Familiar with ISAs such as RISC-V or ARM (THUMB).
• Experience addressing multi-clock and multi-power domain challenges.
• Proficient in Python or Perl for flow automation.
• Exposure to advanced semiconductor process technologies.

Responsibilities

• Architect and author RTL for high-performance digital logic blocks.
• Implement multi-clock domain crossing and multi-power domain strategies.
• Optimize D designs for PPA constraints.
• Lead design debug and support post-silicon bring-up.
• Collaborate with DFT, Physical Design, Verification, Emulation, and Firmware teams.
• Create and maintain design specifications.

Skills

ASIC/SoC design

RTL design

ISAs familiarity

Multi-clock/multi-power domain

Python/Perl scripting

Education

Bachelor's or Master’s in EE/CE

Tools

SystemVerilog

Verilog

Python

Perl

Job description

Staff Microcontroller Subsystem Design Engineer - Ireland - EU Relocation Offered

We are seeking a Staff Microcontroller Subsystem Design Engineer to join a premier IP engineering team. This role is central to driving embedded processing solutions—spanning security, power management, and core system functions—across diverse product portfolios including IoT, Mobile, Automotive, XR, and Compute platforms. You will shape next-generation digital architectures, driving micro-architecture definitions and RTL implementation through to silicon bring-up.

Key Responsibilities

• Architect and author high-performance, low-latency, and low-power RTL for both simple and complex digital logic blocks.
• Implement multi-clock domain crossing (CDC) and multi-power domain strategies for advanced SoC integration.
• Optimize digital designs across Power, Performance, and Area (PPA) constraints.
• Lead execution debugging during design phases and support post-silicon validation and bring-up.
• Partner closely with DFT, Physical Design/Implementation, Verification, Emulation, and Firmware teams.
• Create and maintain comprehensive technical design specifications.

Required Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• 5+ years of hands-on ASIC / SoC digital design experience.
• Deep experience in RTL development using SystemVerilog or Verilog.
• Technical familiarity with modern Instruction Set Architectures (ISAs) such as RISC-V or ARM (including THUMB).
• Practical experience handling multi-clock and multi-power domain design challenges.
• Strong scripting capability using Python or Perl for flow automation.
• Exposure to lower-node advanced semiconductor process technologies.