Staff Subsystem Design Engineer - RTL & IP Expert (Hybrid)

Arm; Cambridge; Hybrid; GBP 97,000 - 132,000; Full time

Job summary

Arm’s IP and Technology team in Solutions Engineering seeks a Staff Subsystem Design Engineer to develop and integrate complex IP and compute subsystems, delivering high-quality RTL designs and microarchitectures. You will refine specs with architects, create IP blocks, and collaborate across verification, implementation, and power teams to meet timing, area and power goals.

You will join a diverse global group of engineers, contributing to advanced subsystem solutions for edge, physical, and

Qualifications

• Bachelor's/Master's/PhD in Electrical Engineering, Electronics Engineering, Computer Engineering or related field.
• 10+ years of relevant industry experience.
• Experience with digital RTL design and microarchitecture.

Responsibilities

• Analyse architectural and system specifications and refine solutions with architects.
• Develop subsystem and IP microarchitecture specifications from high-level requirements.
• Design new IP and subsystem logic and integrate Arm and third-party IP.
• Understand IP interfaces and system interactions for robust integration.
• Develop and maintain design intent, including UPF and timing constraints.
• Perform and drive design quality checks including Lint, CDC, RDC and X-propagation.
• Collaborate with verification teams to review test plans and debug issues.
• Coordinate with implementation, performance and power teams to meet requirements.
• Improve design methodologies and flows and plan work for timely delivery.
• Provide technical guidance and design reviews within the team.

Skills

SystemVerilog

RTL design

Microarchitecture

AMBA AXI/APB

SVA/UVM

Static design checks

Power management

Clock/power gating

Teamwork

Debug and verification

Education

Electrical/Electronic/Computer Engineering degree

Tools

UVM

SVA

Job description

Arm’s IP and Technology team in Solutions Engineering seeks a Staff Subsystem Design Engineer to develop and integrate complex IP and compute subsystems, delivering high-quality RTL designs and microarchitectures. You will refine specs with architects, create IP blocks, and collaborate across verification, implementation, and power teams to meet timing, area and power goals.

You will join a diverse global group of engineers, contributing to advanced subsystem solutions for edge, physical, and