Senior Subsystem Design Engineer — RTL/IP

Arm; Manchester; Hybrid; GBP 97,000 - 132,000; Full time

Job summary

Arm is seeking a Staff Subsystem Design Engineer to lead RTL and IP integration across Arm architectures and AMBA protocols. You will design microarchitectures, develop subsystem specs, and collaborate with verification and implementation teams to deliver high-quality, power-aware designs.

The role requires 10+ years of RTL/subsystem experience, SystemVerilog proficiency, and strong communication. Hybrid working model in the UK with competitive salary range.

Qualifications

• Bachelor's, Master's or PhD in Electrical/Electronics/Computer Engineering or related field.
• 10+ years of relevant industry experience and proven delivery of sophisticated IP or RTL subsystem designs.
• Strong understanding of RTL design techniques for complex SoC development and familiarity with industry-standard EDA tools.

Responsibilities

• Analyse architectural and system specifications, understand implementation challenges and refine solutions.
• Develop subsystem and IP microarchitecture specifications from high-level requirements.
• Design new IP and subsystem logic, integrate Arm and third-party IP into complete subsystem solutions.
• Understand IP functionality, interfaces and system-level interactions for robust integration.
• Develop and maintain design intent, including UPF and timing constraints.
• Perform design quality checks including Lint, CDC, RDC, X-propagation and synthesis.

Skills

SystemVerilog

RTL design

IP/subsystem design

AMBA AXI/APB

Synthesis & timing analysis

Power management (UPF)

Education

Bachelor/Master/PhD in EE/ Electronics/ Computer Engineering

Tools

EDA tools

Job description

Arm is seeking a Staff Subsystem Design Engineer to lead RTL and IP integration across Arm architectures and AMBA protocols. You will design microarchitectures, develop subsystem specs, and collaborate with verification and implementation teams to deliver high-quality, power-aware designs.

The role requires 10+ years of RTL/subsystem experience, SystemVerilog proficiency, and strong communication. Hybrid working model in the UK with competitive salary range.