Staff Design Engineer

Arm; Sheffield; On-site; GBP 110,000 - 160,000; Full time

Job summary

Arm is seeking an experienced Staff Subsystem Design Engineer to lead RTL design and IP integration for next‑generation Edge/Cloud AI subsystems. You will develop microarchitectures, specify IP interfaces and drive robust subsystem solutions across power, timing and area constraints.

You will collaborate with architecture, verification and implementation teams globally, ensuring high‑quality designs and timely delivery while applying advanced low‑power techniques and standard EDA methodologies.

Qualifications

• Bachelor’s, Master’s or PhD in Electrical/Computer Engineering or related field.
• 10+ years of relevant industry experience in RTL and IP/subsystem design.
• Strong SystemVerilog/Verilog and microarchitecture skills.
• Experience with AMBA protocols and integration of IP into subsystems.

Responsibilities

• Specify, define microarchitectures and RTL for complex IP and subsystems.
• Design, integrate Arm and third‑party IP into complete subsystems.
• Collaborate with architecture, verification and implementation teams.
• Support design quality checks including Lint, CDC, RDC and X‑propagation.
• Drive delivery with consideration of timing, area and power constraints.

Skills

SystemVerilog

RTL design

Microarchitecture

IP integration

AMBA AXI/APB

UVM/SVA

Static checks

Power/Timing/Area

Collaboration

C/C++ basics

Hardware interfaces

Education

Bachelor’s/Master’s/PhD in Electrical/Computer Engineering

Job description

Job Overview

Arm’s IP and Technology team in Solutions Engineering department develop subsystem solutions and SoC IPs for next-generation systems targeting Edge AI, Physical AI and Cloud AI. We work across Arm, bringing together the latest Arm technologies and selected third-party IP, as well as developing our own IP where needed, to deliver highly integrated and optimised solutions.

Staff Subsystem Design Engineer

Job Overview

Arm’s IP and Technology team in Solutions Engineering department develop subsystem solutions and SoC IPs for next-generation systems targeting Edge AI, Physical AI and Cloud AI. We work across Arm, bringing together the latest Arm technologies and selected third-party IP, as well as developing our own IP where needed, to deliver highly integrated and optimised solutions.

We are looking for an experienced, motivated and creative Staff Subsystem Design Engineer with a strong background in RTL, IP design and subsystems. You will work on challenging subsystem designs, developing microarchitectures, designing and integrating IP, and solving complex engineering problems across power, performance, area and implementation.

You will work with a diverse, global group of engineers and collaborate across architecture, verification, implementation and other technology teams to deliver high-quality designs.

Responsibilities

As a Staff Subsystem Design Engineer, you will be involved in the specification, microarchitecture, RTL design and integration of complex IPs and compute subsystems.

Your Key Responsibilities Will Include

• Analyse architectural and system specifications, understand implementation challenges and collaborate with architects to refine solutions.
• Develop subsystem and IP microarchitecture specifications from high-level requirements.
• Design new IP and subsystem logic where required, as well as integrate existing Arm and third-party IP into complete subsystem solutions.
• Understand IP functionality, interfaces and system-level interactions to ensure robust integration within the subsystem.
• Develop and maintain design intent, including UPF and timing constraints, where applicable.
• Perform and drive design quality checks including Lint, CDC, RDC, X-propagation, synthesis and other static design checks.
• Navigate architectural and implementation trade-offs and clearly articulate the rationale behind design decisions.
• Work closely with verification teams to review test plans, support verification and debug complex design issues.
• Collaborate with implementation, performance and power teams to ensure designs meet functional, timing, area, power and performance requirements.
• Improve design methodologies and flows to address evolving subsystem and IP development needs.
• Plan and drive your work to ensure high-quality and timely delivery.
• Provide technical guidance, design reviews and support to other engineers while contributing effectively as part of the wider team.

Required Skills And Experience

In addition to holding a Bachelor's, Master's or PhD degree in Electrical Engineering, Electronics Engineering, Computer Engineering or a related discipline, you will have 10+ years of relevant industry experience and demonstrate:

• Extensive hands-on experience in digital RTL design and microarchitecture development using SystemVerilog and/or Verilog.
• A strong delivery record of sophisticated IP or RTL subsystem designs.
• Deep understanding of RTL design techniques and methodologies for complex subsystem and SoC development.
• Ability to analyse high-level specifications and translate them into efficient and robust microarchitectures.
• Familiarity with industry-standard EDA tools and methodologies.
• Experience with static design checks including Lint, CDC, RDC and X-propagation.
• Experience with synthesis, timing analysis and power-management techniques.
• Understanding of low-power design methodologies, including UPF, clock/power gating and multiple power domains.
• Ability to navigate performance, power, area, timing and complexity trade-offs and clearly articulate the rationale behind engineering decisions.
• Knowledge of on-chip protocols and interfaces including AMBA AXI, APB and streaming interfaces.
• Strong understanding of computer architecture and processor-based systems.
• Knowledge of AI-powered software development tools and scripting workflows, including AI coding assistants such as Codex, GitHub Copilot, or equivalent technologies.
• Excellent communication, collaboration and teamwork skills.
• A self-driven and motivated approach, with the ability to take ownership of complex technical problems and drive them to completion.

Nice To Have Skills And Experience

• Experience with Arm-based designs, Arm System Architectures and AMBA protocols.
• Experience with advanced low-power RTL design and power-aware verification, including power/clock gating, retention and DVFS.
• Proficiency with SystemVerilog Assertions (SVA) and formal verification techniques, and UVM.
• Knowledge of Functional Safety methodologies and safety-related hardware design.
• Experience developing or improving RTL, IP and subsystem design flows and methodologies.
• High-level programming experience such as C/C++.

In Return

You will have the opportunity to apply your engineering experience to challenging subsystem and IP design problems, working with teams across Arm to develop technologies for the next generation of AI systems.

You will be part of