Staff Subsystem Design Engineer – AI IP & SoC

Arm; Sheffield; On-site; GBP 110,000 - 160,000; Full time

Job summary

Arm is seeking an experienced Staff Subsystem Design Engineer to lead RTL design and IP integration for next‑generation Edge/Cloud AI subsystems. You will develop microarchitectures, specify IP interfaces and drive robust subsystem solutions across power, timing and area constraints.

You will collaborate with architecture, verification and implementation teams globally, ensuring high‑quality designs and timely delivery while applying advanced low‑power techniques and standard EDA methodologies.

Qualifications

• Bachelor’s, Master’s or PhD in Electrical/Computer Engineering or related field.
• 10+ years of relevant industry experience in RTL and IP/subsystem design.
• Strong SystemVerilog/Verilog and microarchitecture skills.
• Experience with AMBA protocols and integration of IP into subsystems.

Responsibilities

• Specify, define microarchitectures and RTL for complex IP and subsystems.
• Design, integrate Arm and third‑party IP into complete subsystems.
• Collaborate with architecture, verification and implementation teams.
• Support design quality checks including Lint, CDC, RDC and X‑propagation.
• Drive delivery with consideration of timing, area and power constraints.

Skills

SystemVerilog

RTL design

Microarchitecture

IP integration

AMBA AXI/APB

UVM/SVA

Static checks

Power/Timing/Area

Collaboration

C/C++ basics

Hardware interfaces

Education

Bachelor’s/Master’s/PhD in Electrical/Computer Engineering

Job description

Arm is seeking an experienced Staff Subsystem Design Engineer to lead RTL design and IP integration for next‑generation Edge/Cloud AI subsystems. You will develop microarchitectures, specify IP interfaces and drive robust subsystem solutions across power, timing and area constraints.

You will collaborate with architecture, verification and implementation teams globally, ensuring high‑quality designs and timely delivery while applying advanced low‑power techniques and standard EDA methodologies.