Senior Subsystem Design Engineer - RTL & IP Innovation

Arm; West of England; On-site; GBP 97,000 - 132,000; Full time

Job summary

Arm’s Staff Subsystem Design Engineer role focuses on RTL, IP design and subsystems for next-generation AI-enabled platforms. You will develop microarchitectures and integrate Arm and third-party IP into cohesive subsystems.

You will collaborate across architecture, verification, implementation and power teams to meet timing, area and power goals, while driving design quality through UPF, Lint, CDC checks and robust verification.

Qualifications

• Bachelor's, Master's or PhD in Electrical Engineering, Electronics Engineering, Computer Engineering or related field.
• 10+ years of relevant industry experience.
• Extensive hands-on experience in digital RTL design and microarchitecture with SystemVerilog/Verilog.
• Strong track record of sophisticated IP or RTL subsystem designs.
• Familiarity with Lint, CDC, RDC, X-propagation, synthesis and timing analysis.
• Knowledge of AMBA AXI, APB interfaces and on-chip protocols.
• Understanding of low-power design methods including UPF and clock/power gating.
• Excellent communication and teamwork; self-driven.

Responsibilities

• Analyse architectural and system specs; refine solutions with architects.
• Develop subsystem and IP microarchitecture specifications from high-level requirements.
• Design new IP and subsystem logic; integrate Arm and third-party IP.
• Ensure robust IP functionality, interfaces and system-level interactions.
• Develop and maintain design intent and timing constraints; UPF where applicable.
• Conduct design quality checks: Lint, CDC, RDC, X-propagation, synthesis.
• Collaborate with verification teams on test plans and debugging.
• Coordinate with implementation, performance and power teams to meet constraints.

Job description

Arm’s Staff Subsystem Design Engineer role focuses on RTL, IP design and subsystems for next-generation AI-enabled platforms. You will develop microarchitectures and integrate Arm and third-party IP into cohesive subsystems.

You will collaborate across architecture, verification, implementation and power teams to meet timing, area and power goals, while driving design quality through UPF, Lint, CDC checks and robust verification.