SoC Design Verification Engineer

Dabster Systems Ireland Limited; United Kingdom; Presencial; GBP 65.000 - 95.000; Jornada completa

Descripción de la vacante

Dabster Systems Ireland Limited in the United Kingdom seeks a experienced digital verification engineer to drive subsystem/SoC verification using SystemVerilog and UVM. You will modify testbenches, extend coverage, and develop processor-based C tests for verification of complex SoCs.

You will execute regressions, debug RTL simulations, and collaborate with design and software teams to close functional coverage and validate architectures and peripherals.

Formación

• Strong hands-on experience in digital design verification using SystemVerilog and UVM.
• Experience modifying and debugging existing UVM testbenches and components.
• Understanding of constrained-random verification, coverage, assertions, and checkers.
• Experience at subsystem or SoC level verification.
• Knowledge of SoC architectures, bus protocols, and peripheral interfaces.
• Experience developing embedded C tests for processor-based SoCs.
• Ability to debug RTL simulations with standard tools.
• Experience executing regressions and driving coverage closure.
• Scripting in Python, Perl, or shell; version control workflows.

Responsabilidades

• Subsystem and SoC Functional Verification
• Reuse and enhance SystemVerilog/UVM testbenches
• Develop and verify processor-based C tests
• Run regressions, debug, and close coverage
• Plan verification and collaborate with teams

Conocimientos

SystemVerilog

UVM

Constrained-random

Functional coverage

Assertions

Scoreboards

SoC verification

Bus protocols

Python scripting

Regression debugging

Version control

Herramientas

Simulators

Waveform analysis

Python

Descripción del empleo

Key Responsibilities

1. Subsystem and SoC Functional Verification
2. System Verilog/UVM Testbench Reuse and Enhancement
3. Processor-Based C Test Development and Verification
4. Regression Execution, Debugging, and Coverage Closure
5. Verification Planning and Collaboration

Required Technical Skills

Essential Skills

• Strong hands-on experience in digital design verification using System Verilog and UVM.
• Experience working with existing UVM testbenches, including modifying, extending, and debugging reusable verification components.
• Good understanding of constrained-random verification, functional coverage, assertions, scoreboards, and checkers.
• Experience in subsystem-level or SoC-level functional verification.
• Strong understanding of SoC architectures, bus protocols, register interfaces, and processor-controlled peripherals.
• Experience developing, executing, or debugging embedded C tests for processor-based SoC verification.
• Ability to debug complex RTL simulation failures using industry-standard simulators and waveform debugging tools.
• Experience executing regressions, analyzing failures, and driving functional coverage closure.
• Working knowledge of scripting languages such as Python, Perl, or shell scripting.
• Familiarity with version control systems and verification development workflows