Senior Verification Engineer - UVM & SystemVerilog Expert

Chipright; United Kingdom; Remote; GBP 40,000 - 60,000; Part time

Job summary

A leading technology verification company in the United Kingdom seeks a contractor for verification environments of RTL designs. The candidate should have extensive experience in using hardware verification languages like SystemVerilog or Specman, and must be familiar with UVM methodologies. Understanding end-to-end verification processes and familiarity with tools like Mentor Questasim is essential. Competitive compensation is offered.

Qualifications

• Extensive experience in designing verification environments for complex RTL designs.
• Well-versed in using SystemVerilog or Specman language.
• Must have detailed knowledge of verification methodologies like UVM.

Responsibilities

• Work on UVM based verification of a complex multi-unit System IP product.

Skills

Designing and implementing verification environments

Class based hardware verification languages

Verification methodologies such as UVM

End-to-end verification processes

Constrained random stimulus understanding

Familiarity with Mentor Questasim

Familiarity with GIT

Tools

Synopsys VCS

Cadence Incisive

Job description

A leading technology verification company in the United Kingdom seeks a contractor for verification environments of RTL designs. The candidate should have extensive experience in using hardware verification languages like SystemVerilog or Specman, and must be familiar with UVM methodologies. Understanding end-to-end verification processes and familiarity with tools like Mentor Questasim is essential. Competitive compensation is offered.