Senior AMS DV Engineer - SystemVerilog/UVM

Apple; Greater London; On-site; GBP 60,000 - 80,000; Full time

Job summary

Apple is seeking a Design Verification Engineer for its new London team. This role involves defining verification environments, coding test scenarios, and close collaboration with engineering teams. The ideal candidate will have strong knowledge of System Verilog, UVM, and experience in verification methods. A Master's degree or equivalent experience is preferred. This position offers a chance to work in a creative environment that encourages diversity and innovation.

Qualifications

• Knowledge of System Verilog test‑bench language and UVM.
• Hands-on experience with constrained random verification environments.
• Basic design background in support of verification results analysis.
• Knowledge of Object Oriented Programming (OOP).
• Proficiency in English language is required.

Responsibilities

• Definition and design of self-checking verification environments using SystemVerilog UVM.
• Perform all phases of pre-silicon verification.
• Support lab bring-up and deliver tests for engineering teams.

Skills

System Verilog test‑bench language

UVM (Universal Verification Methodology)

Constrained random verification environments

Object Oriented Programming (OOP)

English proficiency

Education

Master’s degree or PhD in Electrical/Computer Engineering

Tools

C++

Python

Verilog

Job description

Apple is seeking a Design Verification Engineer for its new London team. This role involves defining verification environments, coding test scenarios, and close collaboration with engineering teams. The ideal candidate will have strong knowledge of System Verilog, UVM, and experience in verification methods. A Master's degree or equivalent experience is preferred. This position offers a chance to work in a creative environment that encourages diversity and innovation.