Senior Design Verification Engineer

Baya Systems; Cambridge; Hybrid; GBP 90,000 - 120,000; Full time

Job summary

Baya Systems in Cambridge, UK is seeking a Senior Hardware Verification Engineer to design and implement high‑quality testbenches for configurable IPs across SOCs. The role combines hands‑on verification with collaboration across design and DV teams in a hybrid work model.

You will develop UVM-based testbenches using SystemVerilog, Verilog, and Python, write test plans, and help validate interconnects, caches, memory subsystems, and NOCs within complex IP blocks.

Qualifications

• BS/MS in Electrical/Computer Engineering or CS.
• 8+ years in block/IP/SOC verification with hands-on experience.
• Proficiency in Verilog and SystemVerilog.
• Experience with UVM-based testbenches.
• Familiarity with EDA tools for simulation and debug.
• Knowledge of ARM AMBA AXI, APB, and AHB protocols; CHI a plus.
• Experience with caches, memory subsystems, interconnects, and NOCs.
• Strong problem-solving, communication and collaboration skills.

Responsibilities

• Create test plans for configurable IPs interfacing SOC/interconnects across SOC, chiplet or multi chiplet systems.
• Write UVM/SystemVerilog code to implement test plans, checkers and scoreboards.
• Collaborate with software teams to define and implement configurable testbenches.
• Work with design and DV engineers to implement the test plan, debug failures, close coverage, etc.

Skills

Verilog

SystemVerilog

UVM-based testbenches

Python

Education

BS/MS in Electrical Engineering / Computer Engineering / Computer Science

Tools

Verilog/SystemVerilog simulators

Job description

Job Title: Senior Hardware Verification Engineer

Location: Cambridge, England, United Kingdom (Hybrid possible inside the UK)

About the Role: We are seeking a seasoned Design Verification designer with a strong background in building testbenches and writing test sequences for complex IPs. The ideal candidate will play a key role in shaping our technology portfolio, bringing expertise and creativity to our solutions

Responsibilities :

• Collaborate with design and architecture teams to create test plans for highly configurable IPs meant to provide interconnectivity between components across an SOC, chiplet or multi chiplet systems
• Write UVM/SystemVerilog code to implement the test plan, checkers and scoreboards
• Collaborate with software teams to define and implement configurable testbenches
• Work with design and DV engineers to implement the test plan, debug failures, close coverage, etc.

Qualifications:

• BS/MS in Electrical Engineering, Computer Engineering or Computer Science
• 8+ years and current hands-on experience in block-level/IP-level/SOC-level verification
• Proficiency in Verilog, SystemVerilog
• Familiarity with industry-standard EDA tools for simulation and debug
• Deep experience with UVM-based testbenches
• Experience with modern programming languages like Python
• Knowledge of ARM AMBA protocols such as AXI, APB, and AHB
• Understanding of ARM CHI protocol is a plus
• Experience on working with IPs for caches, cache coherency, memory subsystems, interconnects and NOCs
• Experience with formal verification techniques, emulation platforms is a plus
• Excellent problem-solving skills and attention to detail
• Strong communication and collaboration skills

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