Senior Verification Engineer – Hybrid, Equity & Bonus

Riverlane Ltd; Cambridge; Hybrid; GBP 60,000 - 80,000; Full time

Benefits offered by this job

Annual bonus plan

Private medical insurance

Contributory pension scheme

28 days annual leave

Training and conference budgets

Job summary

A leading quantum computing company in Cambridge is seeking a Verification / Senior Verification Engineer to ensure the quality of high-performance systems. The successful candidate will take ownership of verification plans and design scalable testbenches. Candidates should have commercial experience in verification and familiarity with SystemVerilog. The role includes a comprehensive benefits package and a supportive learning environment, encouraging applications from diverse backgrounds.

Qualifications

• Demonstrable commercial experience in functional verification with ownership of verification planning.
• Proven experience with testbench design using verification frameworks such as UVM/OVM.
• Knowledge of SystemVerilog assertion (SVA).

Responsibilities

• Develop and implement scalable testbenches in SystemVerilog.
• Maintain the design verification environment tracking regressions and quality metrics.
• Collaborate with designers to define verification plans based on specifications.

Skills

Functional verification

Testbench design

SystemVerilog assertion

Programming languages (C, C++, Python)

Communication skills

Job description

A leading quantum computing company in Cambridge is seeking a Verification / Senior Verification Engineer to ensure the quality of high-performance systems. The successful candidate will take ownership of verification plans and design scalable testbenches. Candidates should have commercial experience in verification and familiarity with SystemVerilog. The role includes a comprehensive benefits package and a supportive learning environment, encouraging applications from diverse backgrounds.