Senior Verification Engineer: RTL/UVM for Wireless IP

AccelerComm Ltd; Southampton; On-site; GBP 65,000 - 90,000; Full time

Benefits offered by this job

Competitive salary

Bonus up to 20%

EMI share options

Pension

Private health insurance

Hybrid working

Job summary

AccelerComm Ltd in Southampton, UK seeks a Senior Verification Engineer to drive full lifecycle verification of RTL IP across ASIC/FPGA; you will develop verification plans, create UVM testbenches and support integration and tape-out readiness.

Requirements include 3+ years in digital verification, strong SystemVerilog/UVM, Linux scripting and a collaborative mindset. Hybrid working with a competitive package is offered.

Qualifications

• Degree in Electronic Engineering, Computer Engineering or a related discipline.
• At least 3 years experience verifying digital ASIC and/or FPGA designs.
• Strong SystemVerilog and UVM skills.
• Understanding of RTL design principles and hardware implementation.
• Experience with coverage-driven and assertion-based verification.
• Linux proficiency and scripting skills (Python, Tcl or Bash).
• Strong analytical, debugging and problem-solving skills.
• Experience using AI to accelerate verification without sacrificing quality
• Ability to work across multiple teams

Responsibilities

• Develop verification plans from design and architecture specifications.
• Create and maintain SystemVerilog/UVM verification environments.
• Develop testbenches, assertions, scoreboards and coverage models.
• Execute directed and constrained-random verification.
• Analyse coverage and debug RTL and verification issues.
• Support subsystem and system-level integration activities.
• Contribute to automation, regression and CI workflows.
• Participate in design reviews and verification sign-off.
• Mentor and support junior colleagues

Skills

SystemVerilog

UVM

RTL design principles

Linux scripting

Python

Cross-team collaboration

Debugging & problem-solving

AI-assisted verification

Education

Electronic Engineering or related

Tools

SystemVerilog

UVM

Python

Tcl

Bash

Job description

AccelerComm Ltd in Southampton, UK seeks a Senior Verification Engineer to drive full lifecycle verification of RTL IP across ASIC/FPGA; you will develop verification plans, create UVM testbenches and support integration and tape-out readiness.

Requirements include 3+ years in digital verification, strong SystemVerilog/UVM, Linux scripting and a collaborative mindset. Hybrid working with a competitive package is offered.