Senior FPGA Engineer: Lead RTL & Verification Stock Options

Cambridge Aerospace; Cambridge; On-site; GBP 100,000 - 130,000; Full time

Benefits offered by this job

Competitive compensation and stock | £

Private Medical & Dental

Cycle to work scheme

Job summary

Cambridge Aerospace is seeking a Senior FPGA Engineer to take technical ownership of complex FPGA‑based designs, from architecture through verification and hardware bring‑up. You will be hands‑on in Verilog, simulation and debugging, delivering robust RTL and setting high verification standards.

You will mentor junior engineers and collaborate with hardware, RF and embedded software teams to ensure clean integration of high‑speed digital systems.

Qualifications

• Deep understanding of Clock-domain crossing and reset strategies.
• Pipelined architectures and timing closure.
• FSM design, datapaths, and control logic.
• Experience with modern FPGA tools (Xilinx Vivado; Intel Quartus).
• Design and implementation of DSP blocks.

Responsibilities

• Lead the architecture, design, and implementation of FPGA solutions using Verilog HDL
• Translate system‑level requirements into clear, maintainable RTL architectures
• Own complete design blocks from concept through to deployed hardware
• Review and guide Verilog written by other engineers, setting best practices
• Define and contribute to verification strategies, including self‑checking testbenches
• Support FPGA bring‑up, debugging and performance validation on real hardware
• Work closely with hardware, RF, and embedded software teams to ensure clean integration
• Contribute to technical planning and risk reduction for future designs
• Provide technical mentorship to junior and mid‑level engineers

Skills

Clock-domain crossing

Pipelined architectures

FSM design

RTL debugging

Verilog HDL

Tools

Xilinx Vivado

Intel Quartus

Job description

Cambridge Aerospace is seeking a Senior FPGA Engineer to take technical ownership of complex FPGA‑based designs, from architecture through verification and hardware bring‑up. You will be hands‑on in Verilog, simulation and debugging, delivering robust RTL and setting high verification standards.

You will mentor junior engineers and collaborate with hardware, RF and embedded software teams to ensure clean integration of high‑speed digital systems.