Senior Verification Engineer

AccelerComm Ltd; Southampton; Hybrid; GBP 65,000 - 90,000; Full time

Benefits offered by this job

Competitive salary

Bonus up to 20%

EMI share options

Pension

Private health insurance

Hybrid working

Job summary

AccelerComm Ltd in Southampton, UK seeks a Senior Verification Engineer to drive full lifecycle verification of RTL IP across ASIC/FPGA; you will develop verification plans, create UVM testbenches and support integration and tape-out readiness.

Requirements include 3+ years in digital verification, strong SystemVerilog/UVM, Linux scripting and a collaborative mindset. Hybrid working with a competitive package is offered.

Qualifications

• Degree in Electronic Engineering, Computer Engineering or a related discipline.
• At least 3 years experience verifying digital ASIC and/or FPGA designs.
• Strong SystemVerilog and UVM skills.
• Understanding of RTL design principles and hardware implementation.
• Experience with coverage-driven and assertion-based verification.
• Linux proficiency and scripting skills (Python, Tcl or Bash).
• Strong analytical, debugging and problem-solving skills.
• Experience using AI to accelerate verification without sacrificing quality
• Ability to work across multiple teams

Responsibilities

• Develop verification plans from design and architecture specifications.
• Create and maintain SystemVerilog/UVM verification environments.
• Develop testbenches, assertions, scoreboards and coverage models.
• Execute directed and constrained-random verification.
• Analyse coverage and debug RTL and verification issues.
• Support subsystem and system-level integration activities.
• Contribute to automation, regression and CI workflows.
• Participate in design reviews and verification sign-off.
• Mentor and support junior colleagues

Skills

SystemVerilog

UVM

RTL design principles

Linux scripting

Python

Cross-team collaboration

Debugging & problem-solving

AI-assisted verification

Education

Electronic Engineering or related

Tools

SystemVerilog

UVM

Python

Tcl

Bash

Job description

Senior Verification Engineer

Department: Hardware

Employment Type: Full Time

Location: Southampton, UK

Reporting To: Tom Hollis

Description

Our RTL team delivers efficient ASIC and FPGA implementations of advanced communications algorithms, working across IP development, integration and verification. To support this work, we are looking for a Senior Verification Engineer to support the complete UVM verification of Accelercomm IP.

Responsible for verification of RTL implementations for advanced wireless communications IP and modem subsystems, ensuring designs meet functional, performance and quality requirements prior to FPGA deployment and ASIC tape-out.

Key Responsibilities

• Develop verification plans from design and architecture specifications.
• Create and maintain SystemVerilog/UVM verification environments.
• Develop testbenches, assertions, scoreboards and coverage models.
• Execute directed and constrained-random verification.
• Analyse coverage and debug RTL and verification issues.
• Support subsystem and system-level integration activities.
• Contribute to automation, regression and CI workflows.
• Participate in design reviews and verification sign-off.
• Mentor and support junior colleagues

Skills, Knowledge & Expertise

Required

• Degree in Electronic Engineering, Computer Engineering or a related discipline.
• At least 3 years experience verifying digital ASIC and/or FPGA designs.
• Strong SystemVerilog and UVM skills.
• Understanding of RTL design principles and hardware implementation.
• Experience with coverage-driven and assertion-based verification.
• Linux proficiency and scripting skills (Python, Tcl or Bash).
• Strong analytical, debugging and problem-solving skills.
• Experience using AI to accelerate verification without sacrificing quality
• Ability to work across multiple teams

Desirable

• Experience in 4G/5G, NTN, satellite communications or DSP systems.
• Knowledge of modem architectures and Layer 1 processing.
• Experience with Formal Verification, FPGA prototyping and CI environments.
• Familiarity with MATLAB or equivalent modelling tools.

Job Benefits

• We pay competitive salaries which depend on skills and experience.
• We offer a bonus scheme which pays up to 20% of salary annually, depending on performance.
• This is in addition to EMI share options, issued periodically.
• We offer a range of good quality company benefits including pension and private health insurance.
• Our offices on Southampton Science Park provide a great working environment, with a coffee shop, bike storage, showers, plenty of free parking and EV charging points.
• We operate flexible working hours and offer hybrid working.