Senior Design Verification Engineer

IC Resources; West of England; On-site; GBP 70,000 - 90,000; Full time

Job summary

IC Resources is seeking a Senior Staff Verification Engineer for its Automotive division, taking ownership of IP verification topics for future designs. You will collaborate with a team with a proven track record of delivering IP into Automotive Microcontrollers and define verification plans and coverage strategies.

As a Staff Verification Engineer, you will design SV-UVM test benches, debug complex issues, and contribute to the verification strategy while ensuring quality, safety, and timely

Qualifications

• At least 5 years of verification experience with IP-level focus.
• Expertise in SystemVerilog and UVM for test bench design.
• Familiarity with EDA tools and scripting (Python or Perl).
• Knowledge of ISO26262 and ASIL-D functional safety.

Responsibilities

• Define a verification plan and requirements mapping; develop an SV-UVM test bench.
• Debug failing test cases to root cause.
• Define and write a functional coverage model.
• Participate in reviews to ensure test bench meets quality and sign-off targets (coverage, functional safety).
• Proactively increase efficiency of verification activities and mitigate risks early.
• Contribute to verification strategy and architecture of IP test benches.

Skills

IP verification

SystemVerilog

UVM

Python

Perl

Test bench architecture

Tools

EDA tools

Job description

Great opportunity for a Senior staff Verification Engineer to join a global R&D network.

As a Staff Verification Engineer, you will take ownership of IP verification topics for cutting-edge designs of the future of the company’s Automotive division, while working together with the team who has a proven track record in successful IP deliveries into Automotive Microcontrollers.

Responsibilities

• Define a verification plan, requirements mapping, develop an SV-UVM test bench and solve related potentially complex problems
• Debug failing test cases to root cause
• Define and write a functional coverage model
• Participate in reviews to ensure test bench meets quality and sign-off targets, including coverage, functional safety and test bench qualification
• Proactively help increase efficiency of verification activities and mitigate risks early
• Contribute to enhancing Verification strategy and architecture of IP test benches

Requirements

• At least 5 years of experience in verification, with IP level as mandatory and Subsystem level as an advantage
• Expertise in hardware verification languages, particularly System Verilog and UVM, with the ability to design efficient and effective test bench architectures
• Familiarity with EDA tools for Design and Simulation, as well as scripting languages such as Python or Perl
• Knowledge of functional safety standards, including ISO26262 and ASIL-D requirements