Senior SoC / RTL Design Engineer

Arm; Cambridge; On-site; GBP 73,500 - 99,500; Full time

Job summary

Arm Solutions Engineering delivers complex systems solutions from specifications through FE validation, physical implementation, and Silicon Demonstrators. Join our Front End design team, a key part of Arm's Solutions Engineering, developing complete subsystem solutions (Control Subsystems, GPU Subsystem, Safety‑critical subsystems) and SoC IPs for mobile, server, IoT, automotive and more.

You will write micro-architecture specifications, develop RTL and run design checks, and work with

Qualifications

• Hands-on SystemVerilog/Verilog HDL for RTL design.
• Understanding RTL design for complex SoC development.
• Familiarity with industry-standard EDA tools and methodologies.
• Experience in static design checks, power/clock domain crossing, synthesis.
• Knowledge of computer architecture and processor-based systems.
• Scripting in Python/Perl/Unix shell.
• Ability to write specifications and documentation describing complex designs.

Responsibilities

• Write micro-architecture specifications and develop RTL.
• Run design checks and assist verification team.
• Review test plans and help debug design issues.
• Collaborate with implementation to optimise designs and report status.

Skills

SystemVerilog

RTL design

EDA tools

Design verification

Python scripting

Documentation writing

Communication skills

Job description

Job Overview

Arm Solutions Engineering organization delivers complex solutions from systems specifications, through FE & validation, physical implementation and Silicon Demonstrators.

Join our dynamic Front End design team, a key part of Arm's Solutions Engineering! We are a dedicated group of engineers developing complete subsystem solutions (Control Subsystems, GPU Subsystem, Safety‑critical subsystems) and SoC IPs for a wide range of market segments including mobile, server, IoT, automotive, and more. Our solutions build on the output of Arm IP teams, using the latest IP products from Arm and selected 3rd party vendors to provide fully integrated and optimised designs.

Responsibilities

As a member of the design team, you will be involved in the specification, design and verification of various IPs and compute subsystems. Your key responsibilities will include writing micro‑architecture specifications, developing RTL and running various design checks. Additionally, you will work with the verification team to review test plans and help debug design issues and the implementation team to optimise those designs. You will plan your work, provide tracking and report status to ensure high‑quality and timely delivery.

Required Skills And Experience

• Hands‑on working knowledge of SystemVerilog or Verilog HDL for RTL design
• Solid understanding of RTL design for complex SoC development
• Familiarity with industry‑standard EDA tools and methodologies
• Experience in the following areas: static design checks, power and clock domain crossing, synthesis
• Understanding of the fundamentals of computer architecture and systems and practical experience of working on processor‑based system designs
• Knowledge of scripting e.g. Python, Perl or Unix shell scripting
• Good communication skills and ability to write specifications and documentation describing complex designs

Nice to Have Skills and Experience

• Exposure to Arm‑based designs, Arm System Architectures and AMBA protocols
• High level programming experience such as C/C++ and/or assembly language programming
• Functional Safety / ISO 26262 development and design for RAS
• Experience with power‑aware RTL design methodologies and analysis tools. Low‑power design (UPF/CFP), power/clock gating, retention, DVFS.

Salary Range: £73,500 - £99,500 per year

Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.