Senior RTL Engineer - FPGA/ASIC (Verilog/SystemVerilog/VHDL)

Spectrum IT Recruitment; England; On-site; GBP 60,000 - 90,000; Full time

Job summary

Spectrum IT Recruitment is seeking a Senior Design Engineer to develop digital hardware for high-performance wireless and satellite communications. You will work across FPGA and ASIC design, translating requirements into reliable RTL implementations and collaborating with algorithm, architecture and verification teams.

The role focuses on RTL design using Verilog, SystemVerilog or VHDL, with hands-on responsibilities including testbenches, simulation, and timing/resource/power optimisation,

Qualifications

• Hands-on RTL design experience using Verilog, SystemVerilog or VHDL.

Responsibilities

• Translate system and algorithm requirements into micro-architectures for RTL implementation.
• Develop FPGA and ASIC designs using Verilog, SystemVerilog or VHDL.
• Create testbenches and use simulation tools to validate designs.
• Deploy designs onto FPGA development platforms for validation and integration.
• Contribute to timing, resource and power optimisation.
• Collaborate across design, verification and physical implementation.
• Produce technical documentation and contribute to improvements in engineering processes.

Job description

Spectrum IT Recruitment is seeking a Senior Design Engineer to develop digital hardware for high-performance wireless and satellite communications. You will work across FPGA and ASIC design, translating requirements into reliable RTL implementations and collaborating with algorithm, architecture and verification teams.

The role focuses on RTL design using Verilog, SystemVerilog or VHDL, with hands-on responsibilities including testbenches, simulation, and timing/resource/power optimisation,