Senior Design Engineer

Spectrum IT Recruitment; Cambridge; On-site; GBP 70,000 - 95,000; Full time

Job summary

Spectrum IT Recruitment is working with an innovative technology business developing advanced hardware for next-generation wireless and satellite communications. They’re looking for Senior Design Engineers with RTL design using Verilog, SystemVerilog or VHDL.

You’ll develop digital hardware for high-performance communications systems, working across FPGA and ASIC design, collaborating with algorithm, architecture and verification teams to translate requirements into reliable, efficient hardware

Qualifications

• Hands-on RTL design experience using Verilog, SystemVerilog or VHDL.
• Familiarity with simulation/synthesis tools and timing analysis.

Responsibilities

• Translate system/algorithm requirements into RTL micro-architectures.
• Develop FPGA/ASIC designs using Verilog/SystemVerilog or VHDL.
• Create testbenches and use simulation tools to validate designs.
• Deploy designs onto FPGA development platforms for validation.
• Contribute to timing, resource and power optimisation.
• Collaborate with design, verification and physical implementation teams.
• Produce technical documentation and contribute to engineering process improvements.

Skills

RTL design

Verilog

SystemVerilog

VHDL

Tools

EDA tools

Job description

Spectrum IT Recruitment is working with an innovative technology business developing advanced hardware for next-generation wireless and satellite communications. They’re looking for Senior Design Engineers with a main focus on RTL design using Verilog, SystemVerilog or VHDL.

The Role

You’ll develop digital hardware for high-performance communications systems, working across FPGA and ASIC design. Collaborating with algorithm, architecture and verification teams, you’ll help translate requirements into reliable, efficient hardware implementations.

Key Responsibilities

• Translate system and algorithm requirements into micro-architectures for RTL implementation.
• Develop FPGA and ASIC designs using Verilog, SystemVerilog or VHDL.
• Create testbenches and use simulation tools to validate designs.
• Deploy designs onto FPGA development platforms for validation and integration.
• Contribute to timing, resource and power optimisation.
• Collaborate across design, verification and physical implementation.
• Produce technical documentation and contribute to improvements in engineering processes.

Skills and Experience

The key requirement is hands-on RTL design experience using at least one of Verilog, SystemVerilog or VHDL.

We’re interested in candidates with:

• Knowledge of simulation and synthesis using EDA tools.
• An understanding of timing analysis and hardware resource optimisation.
• Strong problem-solving skills and the ability to collaborate across technical teams.
• The ability to produce clear design and verification documentation.

Any experience with the following would be beneficial:

• Communications or digital signal processing algorithms.
• UVM verification.
• C++ or SystemC modelling.
• High-speed interfaces such as PCIe or JESD.
• Python scripting.
• AMD FPGAs and associated tools, or ASIC backend tools.