Senior RTL Design Engineer, AMS | Digital & DV

Apple Inc.; Greater London; Sur place; GBP 85 000 - 120 000; Plein temps

Résumé du poste

Apple Inc. is seeking a forward-thinking RTL Design Engineer to craft high-performance PHY designs. You will work in the AMS Design Team on digital logic, RTL/Verilog implementation and endian tasks across HW/SW boundaries in a global context.

You will participate in all design phases, from concept to silicon bring-up, collaborating with international teams and supporting DV/ATE environments, with strong emphasis on verification and timing closure.

Qualifications

• Strong knowledge of digital logic design and RTL flows.
• Understanding of analog and full custom circuit design.
• Experience with design verification and self-checking tests.
• Ability to partition HW/SW and work with international teams.
• Excellent written and verbal communication in English.

Responsabilités

• Work with systems team to understand top level requirements and develop specifications.
• Implement the function using Verilog RTL according to specification.
• Partition the function between HW and FW for most efficient implementation.
• Develop RTL and FW to implement the function.
• Perform unit testing on the RTL function; RTL synthesis; equivalence checking; STA.
• Develop FW to support DV and ATE environments.
• Support the DV team by writing self-checking tests as required.

Connaissances

Verilog

Digital logic design

Design for DV/ATE

English proficiency

Formation

Bachelor's/Master's/PhD in Electrical/Computer Engineering

Outils

Verilog RTL

Synthesis/STA tools

Description du poste

Apple Inc. is seeking a forward-thinking RTL Design Engineer to craft high-performance PHY designs. You will work in the AMS Design Team on digital logic, RTL/Verilog implementation and endian tasks across HW/SW boundaries in a global context.

You will participate in all design phases, from concept to silicon bring-up, collaborating with international teams and supporting DV/ATE environments, with strong emphasis on verification and timing closure.