Senior RTL Architect: High-Speed Interconnects (PCIe, CXL)

Arm; Cambridge; Hybrid; GBP 126,000 - 171,000; Full time

Job summary

Arm is seeking an experienced RTL/architecture lead in the UK to own microarchitecture, RTL development, and high-speed interconnect integration across multiple silicon products. You translate requirements into synthesizable RTL and drive RTL creation, subsystem integration, and verification support from concept to final delivery.

You will collaborate with architecture, verification, performance, firmware, physical design, and implementation teams to meet targets for bandwidth, latency, power,

Qualifications

• 8+ years of experience in RTL build, microarchitecture, subsystem integration, or related semiconductor roles.
• Deep hands-on expertise in SystemVerilog and the development of sophisticated, high-performance digital subsystems.
• Deep understanding of PCIe, CXL, and UALink, covering transaction flows, ordering, flow control, retries, error handling, host/device integration, memory expansion, and coherent connectivity.
• Experience with coherent or non-coherent interconnects, cache hierarchies, memory systems, and high-speed I/O subsystems.
• Strong understanding of AXI, CHI, ACE, APB, streaming interfaces, buffering, arbitration, scheduling, and backpressure.
• Experience with CDC, RDC, reset sequencing, low-power build, lint, X-propagation, formal verification, synthesis, timing analysis, and waveform debug.
• Ability to convert architectural requirements into clear microarchitecture documents and high-quality RTL.
• Proven technical leadership, communication, and delivery skills across multi-functional teams.
• Bachelor’s or Master’s degree, or equivalent experience, in Electrical Engineering, Computer Engineering, Computer Science, or a related field.

Responsibilities

• Own the microarchitecture, RTL development, and integration of high-speed interconnect subsystems, including PCIe, CXL, and UALink, across multiple silicon products.
• Translate system and protocol requirements into implementation-ready microarchitecture specifications, interfaces, register definitions, and synthesizable RTL, ensuring detailed execution and delivery.
• Drive the development process from concept through RTL creation, subsystem integration, verification support, synthesis preparation, and final delivery.
• Collaborate with architecture, verification, performance, firmware, physical design, and implementation teams to meet functionality, bandwidth, latency, power, area, and timing targets, encouraging a culture of inclusion and teamwork.
• Analyze traffic patterns, workloads, queue depths, credits, outstanding transactions, and buffer requirements to guide implementation tradeoffs.
• Lead technical reviews, debug cross-functional issues, improve building methodologies, and mentor engineers, ensuring outstanding performance and reliability.

Skills

RTL development

microarchitecture

subsystem integration

SystemVerilog

technical leadership

cross-functional delivery

Education

Bachelor’s or Master’s degree in Electrical Engineering/Computer Engineering/Computer Science or related field

Tools

Formal verification

Job description

Arm is seeking an experienced RTL/architecture lead in the UK to own microarchitecture, RTL development, and high-speed interconnect integration across multiple silicon products. You translate requirements into synthesizable RTL and drive RTL creation, subsystem integration, and verification support from concept to final delivery.

You will collaborate with architecture, verification, performance, firmware, physical design, and implementation teams to meet targets for bandwidth, latency, power,