PRINCIPAL DESIGN ENGINEER – HIGH-SPEED INTERCONNECT

Semiconductor Engineering; Cambridge; On-site; GBP 90,000 - 140,000; Full time

Job summary

Semiconductor Engineering is seeking an experienced engineer to own the microarchitecture, RTL development, and integration of high-speed interconnect subsystems across silicon products. You will translate system requirements into implementation-ready RTL, interfaces, and register definitions, ensuring synthesizable designs.

You will drive the development process from concept through RTL creation, collaborating with architecture, verification, performance, firmware, physical design, and

Qualifications

• Experience in high-speed interconnects (PCIe, CXL) design and verification.
• Ability to translate requirements into synthesizable RTL.
• Exposure to system-level verification and meeting bandwidth/latency targets.

Responsibilities

• Own the microarchitecture, RTL development and integration of high-speed interconnect subsystems (PCIe, CXL, UALink).
• Translate system and protocol requirements into microarchitecture specs, interfaces and RTL definitions.
• Lead development from concept through RTL creation and final delivery with cross-functional teams.
• Analyze traffic patterns and guide tradeoffs to meet performance, power, and timing targets.

Skills

RTL development

Microarchitecture ownership

Collaboration across teams

Performance analysis

Job description

Own the microarchitecture, RTL development, and integration of high-speed interconnect subsystems, including PCIe, CXL, and UALink, across multiple silicon products. Translate system and protocol requirements into implementation-ready microarchitecture specifications, interfaces, register definitions, and synthesizable RTL, ensuring detailed execution and delivery.

Drive the development process from concept through RTL creation, subsystem integration, verification support, synthesis preparation, and final delivery. Collaborate with architecture, verification, performance, firmware, physical design, and implementation teams to meet functionality, bandwidth, latency, power, area, and timing targets, encouraging a culture of inclusion and teamwork.

Analyze traffic patterns, workloads, queue depths, credits, outstanding transactions, and buffer requirements to guide implementation tradeoffs. Lead technical reviews, debug cross-functional issues, improve building methodologies, and mentor engineers, ensuring outstanding performance and reliability.