Principal Design Engineer – High-Speed Interconnect Arm

Semiconductor Engineering; United Kingdom; Remote; GBP 90,000 - 120,000; Full time

Job summary

Semiconductor Engineering is seeking an experienced engineer to own the microarchitecture, RTL development, and integration of high-speed interconnect subsystems across multiple silicon products, including PCIe, CXL, and UALink.

You will translate system and protocol requirements into implementation-ready specifications, interfaces, registers, and synthesizable RTL, while collaborating with architecture, verification, performance, firmware, physical design, and implementation teams to hit

Responsibilities

• Own the microarchitecture, RTL development, and integration of high-speed interconnect subsystems across multiple silicon products, including PCIe, CXL, and UALink.
• Translate system and protocol requirements into implementation-ready microarchitecture specifications, interfaces, registers, and synthesizable RTL.
• Drive development from concept through RTL creation, subsystem integration, verification support, synthesis preparation, and final delivery.
• Collaborate with architecture, verification, performance, firmware, physical design, and implementation teams to meet targets for functionality, bandwidth, latency, power, area, and timing.
• Analyze traffic patterns, workloads, queue depths, credits, outstanding transactions, and buffer requirements to guide implementation tradeoffs; mentor engineers and lead technical reviews.

Job description

Own the microarchitecture, RTL development, and integration of high-speed interconnect subsystems, including PCIe, CXL, and UALink, across multiple silicon products. Translate system and protocol requirements into implementation-ready microarchitecture specifications, interfaces, register definitions, and synthesizable RTL, ensuring detailed execution and delivery.

Drive the development process from concept through RTL creation, subsystem integration, verification support, synthesis preparation, and final delivery. Collaborate with architecture, verification, performance, firmware, physical design, and implementation teams to meet functionality, bandwidth, latency, power, area, and timing targets, encouraging a culture of inclusion and teamwork.

Analyze traffic patterns, workloads, queue depths, credits, outstanding transactions, and buffer requirements to guide implementation tradeoffs. Lead technical reviews, debug cross-functional issues, improve building methodologies, and mentor engineers, ensuring outstanding performance and reliability.

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